Processor register

(Redirected from General-purpose register)

A processor register is a quickly
accessible location available to a computer's
processor.[1] Registers usually consist of a
small amount of fast storage, although
some registers have specific hardware
functions, and may be read-only or write- A register-transfer level (RTL) description of an 8-bit register with
detailed implementation, showing how 8 bits of data can be stored
only. In computer architecture, registers are
by using flip-flops.
typically addressed by mechanisms other
than main memory, but may in some cases
be assigned a memory address e.g. DEC PDP-10, ICT 1900.[2]

Almost all computers, whether load/store architecture or not, load items of data from a larger memory
into registers where they are used for arithmetic operations, bitwise operations, and other operations,
and are manipulated or tested by machine instructions. Manipulated items are then often stored back to
main memory, either by the same instruction or by a subsequent one. Modern processors use either
static or dynamic random-access memory (RAM) as main memory, with the latter usually accessed via
one or more cache levels.

Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to
access data. The term normally refers only to the group of registers that are directly encoded as part of an
instruction, as defined by the instruction set. However, modern high-performance CPUs often have
duplicates of these "architectural registers" in order to improve performance via register renaming,
allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995
with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.

When a computer program accesses the same data repeatedly, this is called locality of reference. Holding
frequently used values in registers can be critical to a program's performance. Register allocation is
performed either by a compiler in the code generation phase, or manually by an assembly language
programmer.

Size
Registers are normally measured by the number of bits they can hold, for example, an 8-bit register, 32-
bit register, 64-bit register, 128-bit register, or more. In some instruction sets, the registers can operate
in various modes, breaking down their storage memory into smaller parts (32-bit into four 8-bit ones, for
instance) to which multiple data (vector, or one-dimensional array of data) can be loaded and operated
upon at the same time. Typically it is implemented by adding extra registers that map their memory into
a larger register. Processors that have the ability to execute single instructions on multiple data are called
vector processors.
Types
A processor often contains several kinds of registers, which can be classified according to the types of
values they can store or the instructions that operate on them:

User-accessible registers can be read or written by machine instructions. The most common
division of user-accessible registers is a division into data registers and address registers.
Control registers are used to set the behaviour of system components such as the CPU.
Data registers can hold numeric data values such as integers and, in some architectures,
floating-point numbers, as well as characters, small bit arrays and other data. In some older
architectures, such as the IBM 704, the IBM 709 and successors, the PDP-1, the PDP-4/PDP-
7/PDP-9/PDP-15, the PDP-5/PDP-8, and the HP 2100, a special data register known as the
accumulator is used implicitly for many operations.
Address registers hold addresses and are used by instructions that indirectly access primary
memory.
Some processors contain registers that may only be used to hold an address or only to hold
numeric values (in some cases used as an index register whose value is added as an offset
from some address); others allow registers to hold either kind of quantity. A wide variety of
possible addressing modes, used to specify the effective address of an operand, exist.
The stack and frame pointers are used to manage the run-time stack. Rarely, other data
stacks are addressed by dedicated address registers (see stack machine).
General-purpose registers (GPRs) can store both data and addresses, i.e., they are combined
data/address registers; in some architectures, the register file is unified so that the GPRs can
store floating-point numbers as well.
Status registers hold truth values often used to determine whether some instruction should or
should not be executed.
Floating-point registers (FPRs) store floating-point numbers in many architectures.
Constant registers hold read-only values such as zero, one, or pi.
Vector registers hold data for vector processing done by SIMD instructions (Single Instruction,
Multiple Data).
Special-purpose registers (SPRs) hold some elements of the program state; they usually
include the program counter, also called the instruction pointer, and the status register; the
program counter and status register might be combined in a program status word (PSW) register.
The aforementioned stack pointer is sometimes also included in this group. Embedded
microprocessors, such as microcontrollers, can also have special function registers
corresponding to specialized hardware elements.
Model-specific registers (also called machine-specific registers) store data and settings related
to the processor itself. Because their meanings are attached to the design of a specific processor,
they are not expected to remain standard between processor generations.
Memory type range registers (MTRRs)
Internal registers are not accessible by instructions and are used internally for processor
operations.
The instruction register holds the instruction currently being executed.
Registers related to fetching information from RAM, a collection of storage registers located on
separate chips from the CPU:
Memory buffer register (MBR), also known as memory data register (MDR)
Memory address register (MAR)
Architectural registers are the registers visible to software and are defined by an architecture. They
may not correspond to the physical hardware if register renaming is being performed by the
underlying hardware.
Hardware registers are similar, but occur outside CPUs.
In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a
pseudo-register in that it is hardwired to always return zero when read (mostly to simplify indexing
modes), and it cannot be overwritten. In Alpha, this is also done for the floating-point register file. As a
result of this, register files are commonly quoted as having one register more than how many of them are
actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition
of a register.

Examples
The following table shows the number of registers in several mainstream CPU architectures. Note that in
x86-compatible processors, the stack pointer (ESP) is counted as an integer register, even though there
are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to
most architectures.

Although all of the below-listed architectures are different, almost all are in a basic arrangement known
as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von
Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.
Architecture GPRs/data+address registers FP registers Notes
All data manipulation instructions
work solely within registers, and data
AT&T Hobbit 0 stack of 7
must be moved into a register before
processing.

8 scalar, 8 vector Scalar data registers can be integer

or floating-point; also 64 scalar
Cray-1[3] 8 scalar data, 8 address (64 elements) scratch-pad T registers and 64
address scratch-pad B registers

4004[4] 1 accumulator, 16 others 0

The A register is an accumulator to

which all arithmetic is done; the H
and L registers can be used in
combination as an address register;
all registers can be used as operands
8008[5] 1 accumulator, 6 others 0
in
load/store/move/increment/decrement
instructions and as the other operand
in arithmetic instructions. There is no
floating-point unit (FPU) available.
The A register is an accumulator to
which all arithmetic is done; the
register pairs B+C, D+E, and H+L can
be used as address registers in some
instructions; all registers can be used
as operands in
load/store/move/increment/decrement
1 accumulator, 1 stack pointer, 6 instructions and as the other operand
8080[6] others
0
in arithmetic instructions. Some
instructions only use H+L; another
instruction swaps H+L and D+E.
Floating-point processors intended
for the 8080 were Intel 8231, AMD
Am9511, and Intel 8232. They were
also readily usable with the Z80 and
similar processors.

iAPX432 0 stack of 6 Stack machine

The 8086/8088, 80186/80188, and

80286 processors, if provided an
8087, 80187 or 80287 co-processor
stack of 8 for floating-point operations, support
an 80-bit wide, 8 deep register stack
16-bit x86[7] 8 (if FP present) with some instructions able to use
registers relative to the top of the
stack as operands; without a co-
processor, no floating-point registers
are supported.
The 80386 processor requires an
80387 for floating-point operations,
stack of 8 (if FP present), later processors had built-in floating-
point, with both having an 80-bit wide,
8 (if SSE/MMX 8 deep register stack with some
IA-32[8] 8
instructions able to use registers
present)
relative to the top of the stack as
operands. The Pentium III and later
had the SSE with additional 128-bit
XMM registers.

FP registers are 128-bit XMM

16 or 32 registers, later extended to 256-bit
x86-64[8][9] 16 (if AVX-512 available) YMM registers with AVX/AVX2 and
512-bit ZMM0–ZMM31 registers with
AVX-512.[10]

Fairchild F8[11] 1 accumulator, 64 scratchpad — Instructions can directly reference the

registers, 1 indirect scratchpad first 16 scratchpad registers and can
Architecture GPRs/data+address registers FP registers Notes
register (ISAR) access all scratchpad registers
indirectly through the ISAR[12]
Geode GX/Media GX/4x86/5x86 is
the emulation of 486/Pentium
compatible processor made by
Cyrix/National Semiconductor. Like
Transmeta, the processor had a
translation layer that translated x86
code to native code and executed it.
It does not support 128-bit SSE
registers, just the 80387 stack of
Geode GX 1 data, 1 address 8 eight 80-bit floating-point registers,
and partially supports 3DNow! from
AMD. The native processor only
contains 1 data and 1 address
register for all purposes and it is
translated into 4 paths of 32-bit
naming registers r1 (base), r2 (data),
r3 (back pointer), and r4 (stack
pointer) within scratchpad SRAM for
integer operations.

A 16-bit processor from the

Taiwanese company Sunplus
Technology, notably used in VTech's
Sunplus μ'nSP 8 (sp, r1-r4, bp, sr, pc) 0 [Link] line of educational video
game consoles, in addition to many
plug-in TV games and off-brand
consoles starting from the mid-2000s.

A 32-bit stack machine processor

developed by VM Labs and
specialized for multimedia. It can be
found on the company's own Nuon
DVD player console line and the
Game Wave Family Entertainment
System from ZaPit games. The
design was heavily influenced by
VM Labs Nuon 0 1
Intel's MMX technology; it contained
a 128-byte unified stack cache for
both vector and scalar instructions.
The unified cache can be divided as
eight 128-bit vector registers or thirty-
two 32-bit SIMD scalar registers
through bank renaming; there is no
integer register in this architecture.
Nios II is based on the MIPS IV
instruction set and has 31 32-bit
Nios II[13][14] 31 8 GPRs, with register 0 being
hardwired to zero, and eight 64-bit
floating-point registers

Motorola
2 data, 1 index, 1 stack 0
6800[15]

Address register 8 (a7) is the stack

8 pointer. 68000, 68010, 68012, 68020,
8 data (d0–d7), 8 address (a0–
Motorola 68k[16] a7) (if FP present) and 68030 require an FPU for
floating-point; 68040 had FPU built in.
FP registers are 80-bit.

SH 16-bit 16 6
Architecture GPRs/data+address registers FP registers Notes

The Emotion Engine's main core

(VU0) is a heavily modified DSP
general core intended for general
background tasks and it contains one
64-bit accumulator, two general data
registers, and one 32-bit program
counter. A modified MIPS III
executable core (VU1) is for game
data and protocol control, and it
contains thirty-two 32-bit general-
purpose registers for integer
32 SIMD (integrated in computation and thirty-two 128-bit
UV1) SIMD registers for storing SIMD
instructions, streaming data value
+ 2 × 32 Vector
and some integer calculation value,
Emotion Engine 3(VU0)+ 32(VU1) (dedicated vector co- and one accumulator register for
processor located connecting general floating-point
computation to the vector register file
nearby its GPU) on the co-processor. The coprocessor
is built via a 32-entry 128-bit vector
register file (can only store vector
values that pass from the
accumulator in the CPU) and no
integer registers are built in. Both the
vector co-processor (VPU 0/1) and
the Emotion Engine's entire main
processor module (VU0 + VU1 +
VPU0 + VPU1) are built based on a
modified MIPS instructions set. The
accumulator in this case is not
general-purpose but control status.

Earlier generations allowed up to

127/63 registers per thread
(Tesla/Fermi). The more registers are
configured per thread, the fewer
threads can run at the same time.
CUDA[17] configurable, up to 255 per thread
Registers are 32 bits wide; double-
precision floating-point numbers and
64-bit pointers therefore require two
registers. It additionally has up to 8
predicate registers per thread.[18]
8 'A' registers, A0–A7, hold 18-bit
addresses; 8 'B' registers, B0–B7,
hold 18-bit integer values (with B0
permanently set to zero); 8 'X'
registers, X0–X7, hold 60 bits of
integer or floating-point data. Seven
of the eight 18-bit A registers were
CDC 6000 coupled to their corresponding X
16 8 registers: setting any of the A1–A5
series[19]
registers to a value caused a memory
load of the contents of that address
into the corresponding X register.
Likewise, setting an address into
registers A6 or A7 caused a memory
store into that location in memory
from X6 or X7. (Registers A0 and X0
were not coupled like this).

System/360,[20] 16 4 (if FP present); FP was optional in System/360, and

System/370,[21] always present in S/370 and later. In
16 in G5 and later processors with the Vector Facility,
System/390,
z/Architecture[22]
S/390 models and there are 16 vector registers
z/Architecture containing a machine-dependent
number of 32-bit elements.[23] Some
registers are assigned a fixed
purpose by calling conventions; for
example, register 14 is used for
subroutine return addresses and, for
ELF ABIs, register 15 is used as a
Architecture GPRs/data+address registers FP registers Notes
stack pointer. The S/390 G5
processor increased the number of
floating-point registers to 16.[24]
An instruction set designed by
MMIX[25] 256 256 Donald Knuth in the late 1990s for
pedagogical purposes.

8
NS320xx[26] 8 (if FP present)

A 32/40-bit stack machine-based

network processor with a modified
Xelerated X10 1 32
MIPS instruction set and a 128-bit
floating-point unit.

An eight-core 8/16-bit sliced stack

machine controller with a simple logic
circuit inside, it has 8 cog counters
(cores), each containing three 8/16
bit special control registers with 32 bit
x 512 stack RAM. However, it does
not contain any general register for
integer purposes. Unlike most
Parallax
0 2 shadow register files in modern
Propeller
processors and multi-core systems,
all of the stack RAM in cog can be
accessed in instruction level, which
allows all of these cogs to act as a
single general-purpose core if
necessary. Floating-point unit is
external and it contains two 80-bit
vector registers.
And 64 1-bit predicate registers and 8
Itanium[27] 128 128 branch registers. The FP registers
are 82-bit.

Global register 0 is hardwired to 0.

SPARC[28] 31 32
Uses register windows.

Also included are a link register, a

IBM POWER 32 32 count register, and a multiply quotient
(MQ) register.
Also included are a link register and a
PowerPC/Power count register. Processors supporting
32 32
ISA[29] the Vector facility also have 32 128-
bit vector registers.

Also included are a stack pointer and

a frame pointer. Additional registers
Blackfin[30] 8 data, 2 accumulator, 6 address 0 are used to implement zero-overhead
loops and circular buffer DAGs (data
address generators).
128 general purpose registers, which
IBM Cell SPE 128 can hold integer, address, or floating-
point values[31]

PDP-10 16 All of the registers may be used

generally (integer, float, stack pointer,
jump, indexing, etc.). Every 36-bit
memory (or register) word can also
be manipulated as a half-word, which
can be considered an (18-bit)
address. Other word interpretations
are used by certain instructions. In
the original PDP-10 processors,
these 16 GPRs also corresponded to
main (i.e. core) memory locations 0–
15; a hardware option called "fast
Architecture GPRs/data+address registers FP registers Notes
memory" implemented the registers
as separate ICs, and references to
memory locations 0–15 referred to
the IC registers. Later models
implemented the registers as "fast
memory" and continued to make
memory locations 0–15 refer to them.
Movement instructions take (register,
memory) operands: MOVE 1,2 is
register-register, and MOVE 1,1000
is memory-to-register.

6 R7 is the program counter. Any

register can be a stack pointer but R6
PDP-11 7 (if FPP present) is used for hardware interrupts and
traps.
The general purpose registers are
used for floating-point values as well.
Three of the registers have special
VAX[32] 16 uses: R12 (Argument Pointer), R13
(Frame Pointer), and R14 (Stack
Pointer), while R15 refers to the
Program Counter.

Registers R31 (integer) and F31

Alpha[33] 31 31
(floating-point) are hardwired to zero.

6502's content A (Accumulator)

register for main purpose data store
and memory address (8-bit data/16-
6502 1 data, 2 index 0 bit address), X and Y are indirect and
direct index registers (respectively)
and the SP registers are specific
index only.
65c816 is the 16-bit successor of the
6502. X, Y, and D (Direct Page
register) are condition registers and
SP register are specific index only.
Main accumulator extended to 16-bit
W65C816S 1 0
(C)[34] while keeping 8-bit (A) for
compatibility and main registers can
now address up to 24-bit (16-bit wide
data instruction/24-bit memory
address).

Media-embedded processor was a

32-bit processor developed by
Toshiba with a modded 8080
instruction set. Only the A, B, C, and
MeP 4 8 D registers are available through all
modes (8/16/32-bit). It is incompatible
with x86; however, it contains an 80-
bit floating-point unit that is x87-
compatible.
PIC
1 0
microcontroller

AVR
32 0
microcontroller

r15 is the program counter, and not

usable as a general purpose register;
r13 is the stack pointer; r8–r13 can
ARM 32-bit Varies be switched out for others (banked)
(ARM/A32, 14 (up to 32) on a processor mode switch. Older
Thumb-2/T32) versions had 26-bit addressing,[35]
and used upper bits of the program
counter (r15) for status flags, making
that register 32-bit.
 Architecture GPRs/data+address registers FP registers Notes

Version 1 of Thumb, which only

ARM 32-bit supported access to registers r0
8 16
(Thumb)
through r7[36]

ARM 64-bit Register r31 is the stack pointer or

31 32 hardwired to 0, depending on the
(A64) [37] context.

MIPS[38] 31 32 Integer register 0 is hardwired to 0.

Integer register 0 is hardwired to 0.

[39] The RV32E variant, intended for
RISC-V 31 32
systems with very limited resources,
has 15 integer registers.
Each instruction controls whether
registers are interpreted as integers
or single precision floating point.
Epiphany 64 (per core)[40] Architecture is scalable to 4096 cores
with 16 and 64 core implementations
currently available.

Usage
The number of registers available on a processor and the operations that can be performed using those
registers has a significant impact on the efficiency of code generated by optimizing compilers. The
Strahler number of an expression tree gives the minimum number of registers required to evaluate that
expression tree.

See also
CPU cache
Quantum register
Register allocation
Register file
Shift register

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