Computer Organization

and Architecture
ITT 303
Instruction Set Architecture: Registers, Instructions,
Addressing Modes, Condition Codes

Dr. Janibul Bashir

NIT Srinagar
Autumn 2023

https://www.janibbashir.com/coa-autumn2023
ISA vs Microarchitecture

■ Computer Architecture: The science and art of designing, selecting, and

interconnecting hardware components and designing the hardware/software
interface to create a computing system that meets functional, performance,
energy consumption, cost, and other specific goals.
■ Architecture: The view of a computer as presented to software designers – ISA
(Instruction set architecture) -- Interface b/w HW and SW
■ Organization: The actual implementation of a computer in hardware. –
microarchitecture

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What is a computer?

A computer is a general purpose device that can be programmed to process

information, and yield meaningful results.

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Working
Three key components
• Computation
Information • Communication
Program • Storage (memory)
store

Computer

results

■ Program – List of instructions given to the computer

■ Information store – data, images, files, videos
■ Computer – Process the information store according to
the instructions in the program
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ISA vs. Microarchitecture
■ ISA
❑ Agreed upon interface between software and Problem
hardware
Algorithm
■ SW/compiler assumes, HW promises
Program
❑ What the software writer needs to know to write ISA
and debug system/user programs
Microarchitecture
■ Microarchitecture Circuits
❑ Specific implementation of an ISA Electrons
❑ Not visible to the software
■ Microprocessor
❑ ISA, uarch, circuits
❑ “Architecture” = ISA + microarchitecture
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ISA vs. Microarchitecture
■ What is part of ISA vs. Uarch?
❑ Gas pedal: interface for “acceleration”
❑ Internals of the engine: implement “acceleration”

■ Implementation (uarch) can be various as long as it satisfies the

specification (ISA)
❑ Add instruction vs. Adder implementation
■ Bit serial, ripple carry, carry lookahead adders are all part of microarchitecture
❑ x86 ISA has many implementations: 286, 386, 486, Pentium, Pentium Pro,
Pentium 4, Core, …

■ Microarchitecture usually changes faster than ISA

❑ Few ISAs (x86, ARM, SPARC, MIPS, Alpha) but many uarchs
❑ Why?

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ISA Components
■ Instructions
❑ Opcodes, Addressing Modes, Data Types
❑ Instruction Types and Formats
❑ Registers, Condition Codes
■ Memory
❑ Address space, Addressability, Alignment
❑ Virtual memory management
■ Call, Interrupt/Exception Handling
■ Access Control, Priority/Privilege
■ I/O: memory-mapped vs. instr.
■ Task/thread Management
■ Power and Thermal Management
■ Multi-threading support, Multiprocessor support

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Microarchitecture
■ Implementation of the ISA under specific design constraints and goals
■ Anything done in hardware without exposure to software
❑ Pipelining
❑ In-order versus out-of-order instruction execution
❑ Memory access scheduling policy
❑ Speculative execution
❑ Superscalar processing (multiple instruction issue?)
❑ Clock gating
❑ Caching? Levels, size, associativity, replacement policy
❑ Prefetching?
❑ Voltage/frequency scaling?
❑ Error correction?

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 Memory
View of Memory
❑ One large array of memory cells. Each cell can store a single bit 0 or 1.
❑ A group of bits can be stored or retrieved in a single operation - word, wordlength
❑ Address space: How many uniquely identifiable locations in memory.
❑ Addressability: How much data does each uniquely identifiable location store
❑ Byte addressable: most ISAs, characters are 8 bits - Each byte has an address
❑ Bit addressable: Burroughs 1700. Why?
❑ 64-bit addressable: Some supercomputers. Why?
❑ 32-bit addressable: First Alpha
❑ Food for thought
❑ How do you add 2 32-bit numbers with only byte addressability?
❑ How do you add 2 8-bit numbers with only 32-bit addressability?
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 Memory
Storage of Data in Memory
■ Data Types
❑ char (1 byte), short (2 bytes), int (4 bytes), long int (8 bytes)

■ How are multibyte variables stored in memory ?

❑ Example : How is a 4 byte integer stored ?
❑ Save the 4 bytes in consecutive locations
❑ Little endian representation (used in ARM and x86) → The LSB is stored in
the lowest location
❑ Big endian representation (Sun Sparc, IBM PPC) → The MSB is stored in the
lowest location

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 Memory
Little Endian vs Big Endian

Big endian
87 65 43 21
0 1 2 3
0x87654321
Little endian
21 43 65 87
0 1 2 3

■ Note the order of the storage of bytes

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 Memory
Storage of Arrays in Memory
■ Single dimensional arrays. Consider an array of integers : a[100]

a[0] a[1] a[2]

■ Each integer is stored in either a little endian or big endian format
■ 2 dimensional arrays :
❑ int a[100][100]
❑ float b[100][100]
❑ Two methods : row major and column major

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 Memory
Row Major vs Column Major
■ Row Major (C, Python)
❑ Store the first row as an 1D array
❑ Then store the second row, and so on...
■ Column Major (Fortran, Matlab)
❑ Store the first column as an 1D array
❑ Then store the second column, and so on
■ Multidimensional arrays
❑ Store the entire array as a sequence of 1D arrays

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The Von Neumann Model/Architecture
■ Also called stored program computer (instructions in memory). Two
key properties:

❑ Stored program
■ Instructions stored in a linear memory array
■ Memory is unified between instructions and data
❑ The interpretation of a stored value depends on the control signals
When is a value interpreted as an instruction?
❑ Sequential instruction processing
■ One instruction processed (fetched, executed, and completed) at a time
■ Program counter (instruction pointer) identifies the current instr.
■ Program counter is advanced sequentially except for control transfer instructions

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 Instruction set
Instruction Set
The semantics of all the instructions supported by a processor is known as its instruction set
architecture (ISA). This includes the semantics of the instructions themselves, along with their
operands, and interfaces with peripheral devices.

❑ Registers
❑ Instructions
❑ Instruction Sequencing
❑ Addressing Modes
❑ Condition Codes

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 Instruction set
View of Registers
■ Registers → named storage locations
❑ in ARM : r0, r1, … r15
❑ in x86 : eax, ebx, ecx, edx, esi, edi
■ Machine specific registers (MSR)
❑ Examples : Control the machine such as the speed of fans, power control
settings
❑ Read the on-chip temperature.
■ Registers with special functions :
❑ stack pointer
❑ program counter
❑ return address

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 Instruction set
Why Registers?
■ Registers
❑ How many
❑ Size of each register

■ Why is having registers a good idea?

❑ Because programs exhibit a characteristic called data locality
❑ A recently produced/accessed value is likely to be used more than once
(temporal locality)
■ Storing that value in a register eliminates the need to go to memory each
time that value is needed

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 Instruction set
Programmer Visible (Architectural) State

M[0]
M[1]
M[2]
M[3] Registers
M[4] - given special names in the ISA
(as opposed to addresses)
- general vs. special purpose

M[N-1]
Memory Program Counter
array of storage locations
indexed by an address memory address
of the current instruction
Instructions (and programs) specify how to transform
the values of programmer visible state
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 Instruction set
Aside: Programmer Invisible State
■ Microarchitectural state
■ Programmer cannot access this directly

■ E.g. cache state

■ E.g. pipeline registers

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 Instruction set
Evolution of Register Architecture
■ Accumulator
❑ a legacy from the “adding” machine days

■ Accumulator + address registers

❑ need register indirection
❑ initially address registers were special-purpose, i.e., can only
be loaded with an address for indirection
❑ eventually arithmetic on addresses became supported

■ General purpose registers (GPR)

❑ all registers good for all purposes
❑ grew from a few registers to 32 (common for RISC) to 128 in
Intel IA-64

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 Instruction set
Instructions and Instruction Sequencing
❑ A computer must have instructions capable of performing four types of operations:
❑ Data transfers between the memory and the processor registers
❑ Arithmetic and logic operations on data
❑ Program sequencing and control
❑ I/O transfers operand 1 operand n
Instruction operand 2

■ instruction or opcode
❑ textual identifier of a machine instruction
■ operand
❑ constant (also known as an immediate)
❑ register
❑ memory location
■ To facilitate the discussion let us first discuss two important notations - Register Transfer Notation and
Assembly Language Notation
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Dataflow Model (of a Computer)
■ Von Neumann model: An instruction is fetched and executed in control flow
order
❑ As specified by the instruction pointer
❑ Sequential unless explicit control flow instruction

■ Dataflow model: An instruction is fetched and executed in data flow order

❑ i.e., when its operands are ready
❑ i.e., there is no instruction pointer
❑ Instruction ordering specified by data flow dependence
■ Each instruction specifies “who” should receive the result
■ An instruction can “fire” whenever all operands are received
❑ Potentially many instructions can execute at the same time
■ Inherently more parallel

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 Instruction set
Register Transfer Notation
■ This notation allows us to specify the semantics of instructions
■ r1 ← [r2]
❑ transfer the contents of register r2 to register r1

■ r1 ← [r2] + 4
❑ add 4 to the contents of register r2, and transfer the contents to register r1

■ r1 ← [[r2]]
❑ access the memory location that matches the contents of r2, and store the data in register r1

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 Instruction set
What is Assembly Language

* A low level programming language uses simple statements that correspond to typically
just one machine instruction. These languages are specific to the ISA.
* The term “assembly language” refers to a family of low-level programming languages that
are specific to an ISA. They have a generic structure that consists of a sequence of
assembly statements.
* Typically, each assembly statement has two parts: (1) an instruction code that is a
mnemonic for a basic machine instruction, and (2) and a list of operands.

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 Instruction set
Why learn Assembly Language ?

■ Software developers' perspective

❑ Write highly efficient code
■ Suitable for the core parts of games, and mission critical software

❑ Write code for operating systems and device drivers

❑ Use features of the machine that are not supported by
standard programming languages

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 Instruction set
Assemblers

■ Assemblers are programs that convert programs written in

low level languages to machine code (0s and 1s)
■ Examples :
❑ nasm, tasm, and masm for x86 ISAs
❑ On a linux system try :
■ gcc -S <filename.c>
■ filename.s is its assembly representation
■ Then type: gcc filename.s (will generate a binary: a.out)

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 Instruction set
Hardware Designers Perspective

■ Learning the assembly language is the same as learning the

intricacies of the instruction set
■ Tells HW designers : what to build ?

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 Instruction set
Examples of Instructions

sub r3, r1, r2

mul r3, r1, r2

■ subtract the contents of r2 from the contents of

r1, and save the result in r3
■ multiply the contents of r2 with the contents of
r1, and save the results in r3

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 Instruction set
Features of an ISA
* Complete
* It should be able to implement all the programs that users may write.
* Concise
* The instruction set should have a limited size. Typically an ISA contains 32-1000
instructions.
* Generic
* Instructions should not be too specialized, e.g. add14 (adds a number with 14)
instruction is too specialized
* Simple
* Should not be very complicated.

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 Instruction set
Designing an ISA
* Important questions that need to be answered :
* How many instructions should we have ?
* What should they do ?
* How complicated should they be ?

Two different paradigms : RISC and CISC

Close to hardware Close to Programmer

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 Instruction set
RISC vs CISC - I

A reduced instruction set computer (RISC) implements

simple instructions that have a simple and regular
structure (occupy single word). The number of instructions
is typically a small number (64 to 128).
Examples: ARM, IBM PowerPC,HP PA-RISC

A complex instruction set computer (CISC) implements complex

instructions that are highly irregular, take multiple operands, and
implement complex functionalities. Secondly, the number of
instructions is large (typically
500+). Examples: Intel x86, VAX

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 Instruction set
RISC vs CISC - II
■ RISC machines follow load/store architecture whereas CISC follow
memory/memory architecture.
■ Load/store vs. memory/memory architectures

❑ Load/store architecture: operate instructions operate only on registers and they use
load and store instructions to access the memory.
■ E.g., MIPS, ARM and many RISC ISAs

❑ Memory/memory architecture: operate instructions can operate on memory

locations
■ E.g., x86, VAX and many CISC ISAs

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 Instruction sequencing
Instruction Sequencing - I
■ All the instructions are initially placed in the computer memory - stored
program execution.
■ Instructions are fetched and executed in control flow order
❑ As specified by the instruction pointer or program counter (stores address of the
next instruction to be executed).
❑ The instrucion fetched from memory is placed in register called Instruction
Register.
❑ Sequential or straight line execution unless explicit control flow instruction
(branch instructions).
❑ Branch instruction may load a new address in the PC (branch target address).
❑ Conditional Branch and Unconditional Branch.

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 Instruction sequencing
Instruction Sequencing - II
❑ Or an instruction is fetched and executed in data flow order
❑ i.e., when its operands are ready
❑ i.e., there is no instruction pointer
❑ Instruction ordering specified by data flow dependence
■ Each instruction specifies “who” should receive the result
■ An instruction can “fire” whenever all operands are received
❑ Potentially many instructions can execute at the same time
■ Inherently more parallel

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 Instruction sequencing
Instruction Processing Style
❑ Specifies the number of “operands” an instruction “operates” on and how it does
so
❑ 0, 1, 2, 3 address machines
■ 0-address: stack machine (push A, pop A, op)
■ 1-address: accumulator machine (ld A, st A, op A)
■ 2-address: 2-operand machine (one is both source and dest)
■ 3-address: 3-operand machine (source and dest are separate).
■ Specify the operands to an instruction - Addressing modes
❑ Helps to locate the operands.
❑ Determines the access mechanism.

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 Addressing Modes
Addressing Modes
■ The different ways for specifying the locations of instruction operands are known as addressing modes.
■ Let V be the value of an operand, and let r1, r2 specify registers
■ Immediate addressing mode
❑ V ← imm , e.g. 4, 8, 0x13, -3

■ Register direct addressing mode

❑ V ← r1
❑ e.g. r1, r2, r3 …

■ Register indirect
❑ V ← [r1]

■ Base-offset or index : V ← [r1 + offset], e.g. 20[r1] (V ← [20+r1])

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 Addressing Modes
Register Indirect Mode
■ V ← [r1]

r1

value
register file

memory

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 Addressing Modes
Base-offset Addressing Mode

■ V ← [r1+offset]

r1
offset

value
register file

memory

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 Addressing Modes
Addressing Modes - II
■ Base-index-offset
❑ V ← [r1 + r2 + offset]
❑ example: 100[r1,r2] (V ← [r1 + r2 + 100])

■ Memory Direct
❑ V ← [addr]
❑ example : [0x12ABCD03]

■ PC Relative
❑ V ← [pc + offset]
❑ example: 100[pc] (V ← [pc + 100])

■ Auto-Increment and Auto-Decrement

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 Addressing Modes
Base-Index-Offset Addressing Mode

■ V ← [r1+r2 +offset]

r1
offset
r2
value
register file

memory
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 Addressing Modes
Benefits of Different Addressing Modes
■ Another example of programmer vs. microarchitect tradeoff

■ Advantage of more addressing modes:

❑ Enables better mapping of high-level constructs to the machine: some accesses are
better expressed with a different mode 🡪 reduced number of instructions and code
size
■ Think array accesses (autoincrement mode)
■ Think indirection (pointer chasing)
■ Sparse matrix accesses

■ Disadvantage:
❑ More work for the compiler
❑ More work for the microarchitect

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 Addressing Modes
ISA Orthogonality
■ Orthogonal ISA:
❑ All addressing modes can be used with all instruction types
❑ Example: VAX
■ (~13 addressing modes) x (>300 opcodes) x (integer and FP formats)

■ Who is this good for?

■ Who is this bad for?

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 Condition Codes
Condition Codes
■ Processor needs to store the status of the different operations.
■ This information is required subsequently by the branch instructions.
■ This is accomplished by recording the required information in individual bits,
often called condition code flags.
■ These flags are usually grouped together in a special processor register called
the condition code register or status register.
■ N (negative)
■ Z (zero)
■ V (overflow)
■ C (carry)

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Many Different ISAs Over Decades
■ x86
■ PDP-x: Programmed Data Processor (PDP-11)
■ VAX
■ IBM 360
■ CDC 6600
■ SIMD ISAs: CRAY-1, Connection Machine
■ VLIW ISAs: Multiflow, Cydrome, IA-64 (EPIC)
■ PowerPC, POWER
■ RISC ISAs: Alpha, MIPS, SPARC, ARM
■ What are the fundamental differences?
❑ E.g., how instructions are specified and what they do
❑ E.g., how complex are the instructions

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END

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