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IN THIS ISSUE
FEATURES
10 What’s the Difference Between
the Enterprise and Consumer
Metaverses?
The enterprise metaverse is a Fortnite but for digital
twins. Presented is a perspective for developers
on the challenges—and opportunities—ahead.
22
the backing of Ayar Labs, Broadcom, Cisco, Marvell, and NVIDIA.
22
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overvoltage protection is a necessity in virtually any application that
connects to a power line.
EDITORIAL MISSION:
To provide the most current, accurate, and in-depth technical coverage of the key emerging technologies that engineers need to design tomorrow’s products today.
ELECTRONIC DESIGN ISSN 0013-4872 (Print) / 1944-9550 (Digital) is published bi-monthly in Jan/Feb, Mar/Apr, Permission is granted to users registered with the Copyright Clearance Center Inc.
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DIGITAL
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NEW!
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look through a new house
or building—virtually. Or to
HIGH INPUT VOLTAGES remotely design and debug an
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T
he “enterprise metaverse”—the
metaverse for commercial,
industrial infrastructure, and
manufacturing applications—
will be far removed from the social,
gaming, and entertainment ecosystem
that many of us regard today as the
“consumer metaverse,” where entities
like Fortnite and Roblox have staked
Credit: 238554561 @ Irinayeryomina | Dreamstime
an early claim.
We intuitively understand the applica-
tions for a consumer metaverse, where Is it worth double-clicking on what the data itself represents the diversity of
the core mechanics are focused on game we mean by an autonomous system? It’s situations that you want your autonomous
play and socialization. But what are the a mechanical system that knows how to system to respond to.
applications for an enterprise metaverse, respond dynamically to its context. A Collecting this data in the real world
and what are they good for? Today we robot or other mechanical system that’s is often very expensive, time-consuming,
see three main focal points for enterprise not autonomous will do exactly what sometimes dangerous—and in some cases,
metaverse applications emerging from our it’s programmed to do. What makes it virtually impossible. It’s not possible to
engagement with customers: autonomous or semi-autonomous is when order up edge cases on demand, yet they’re
it can make sense of its dynamic envi- exactly what autonomous systems need to
1. Synthetic Data Generation ronment and then act accordingly—and be able to recognize and handle to operate
(Open-Loop Simulation) independently. safely and robustly.
The idea here is to create an environ- But human experience has taught us Thankfully, when driving around town
mental context where virtual sensors are that it can take a long time to learn how to in our vehicles in the real world, traffic
placed either in the environment itself or operate successfully within a new context! accidents seldom happen. Yet that’s exactly
on systems that inhabit it. The goal is to The same is true for machines. The way what you’d want a self-driving car to expe-
collect data—typically, perception data— to accelerate that learning is by expos- rience and learn from. It just doesn’t hap-
for the purpose of training machine- ing autonomous systems to more diverse pen very often.
learning (ML) models, or other forms of information. It’s not enough simply to So how do you go and collect this
autonomous software. generate more data. It’s important that data very intentionally? The enterprise
2. Validation of Autonomous
Systems and Processes Automation
(Closed-Loop Simulation)
We can also think of the enterprise
metaverse in terms of validation and opti-
mization. This differs from Open-Loop
Simulation/Synthetic Data Generation
in that you don’t merely have a virtual
context in which a system is operating;
you also have actuation of those systems.
These systems can run their external soft-
ware brain based on input from virtual
sensors and then determine how they Falcon, Duality’s Digital Twin Simulator, utilizes digital-twin counterparts based off of real-
should respond. And you can test this in life appearance, physics, and behaviors. Photos courtesy of Duality Robotics
a real-time closed-loop simulation.
Thus, you can run many thousands a workflow like that from an operations Digital Twin Challenges
of tests before you ever deploy a system perspective. The three dynamics discussed are what
like this in the real world. Whereas with a The enterprise metaverse holds this we’ve seen most frequently with custom-
self-driving car, a change applied to even promise. For the first time, we’re allowed ers, and all of them can drive significant
just one line of code could make the soft- a fully instrumented environment where business value. Some shift the bottom line,
ware—and vehicle—behave unpredictably a complex set of systems can interact and some the top line, but these are firmly
or even crash (think of how common orchestrate, and subsequently analyze all grounded use cases addressing signifi-
software bugs are…). We obviously can’t of the output data in a closed loop to figure cant pain points for companies today.
afford for this to happen when we intro- out what and where to optimize. Then, In other words, the metaverse future is
duce autonomous systems into real-world we can run A/B tests or myriad configu- already here.
operating environments. rations in parallel to find the optimal It’s a paramount concern to ensure that
How do we ensure that these systems workflow. these autonomous “smart” systems aren’t
are robust and validated? It’s not realis- suddenly going to become “dumb” when
tically possible every time you change 3. B2B2C Interaction you simply change a couple of lines of
a line of code to go drive a thousand In some cases, we want to expose code. It’s also important to allow your
miles for validation. The same applies these digital twins to end customers or customers to interact directly with these
in a construction site or a warehouse. consumers. A simple example: a shav- digital twins so as to get a much better
Every time you change a line of code in ing blade. How do you really show off understanding of them.
your mobile robot’s logic, if that robot is the features of that blade? Until recently, Today there are online product configu-
deployed at 40 customer sites, you can’t manufacturers have invested as much as rators for almost every new automobile,
realistically test that robot at all 40 sites 4X more money in the packaging than a simple example of a digital twin. But it
before you release the software. So, how the shaving blade itself, all to influence can cost half a million to a million dollars
do you actually validate these systems the purchase decision. But how might and six months working with a consulting
effectively? you influence consumers’ purchasing agency to develop one of these configura-
Until recently, we’ve been thinking in decisions when over 90% of those pur- tors. How can we practically do this for
terms of single systems. But now imag- chases are made online? an $8 to $12 product?
ine that in a warehouse, or an airport, we One way is to allow them to interact These are among the many meta-
have a broad collection of systems that directly with a digital twin of your prod- verse challenges that enterprises face
are autonomous, semi-autonomous, or uct, or your service, so that they can more today. They’re not solutions in search
human operated, all working together fully understand and appreciate the value of problems, but rather acute problems
in close orchestration. At this point, it proposition. And this is where the lines that enterprises currently grapple with,
becomes increasingly challenging to between the enterprise metaverse and the and frankly don’t have great solutions to
think about how to go about optimizing consumer metaverse begin to blur. overcome them.
GO TO [Link] 11
Comparing Metaverses
Customer learning
Customers are very comfortable today
working with data and analytics, and har-
nessing them to impact how key decisions
are made. It’s how any successful business
operates today.
AI and ML are just starting to achieve
that level of mainstream understanding
and adoption. Oftentimes, even when
we don’t think we’re using ML, it’s there
under the hood and it’s solving practical
challenges in seamless ways within cur-
rent workflows.
When it comes to digital twins, com-
panies today are just beginning that jour-
From
ney. The tools, pipeline, and plumbing
doesn’t really exist. The early adopters
(brave souls!) will forge the way forward
for everyone else. There’s a significant
learning curve for companies just start-
ing to adopt digital twins in their work-
flows, and it’s best to acknowledge and
plan for that.
GO TO [Link] 13
Comparing Metaverses
Dreamstime | 537587
RoHS
and Its Impact on
the Resistor Industry
R
oHS stands for Restriction of Fully lead-free conditions defined in article 5(1), adapt-
Hazardous Substances. Also ing the Annexes to scientific and techni-
known as Directive 2002/95/
requirements for thick- cal progress. Seven exemption groups have
EC, it originated in the Euro- film chip resistors will been approved for the use of lead in certain
pean Union and restricts the use of specif- inevitably increase in applications under EU RoHS Annex III for
ic hazardous materials found in electrical/ a few more years. Exemption 7c-1 has the
electronic products (known as EEE). All
the next few years. For largest impact on the electric and electronic
applicable products in the EU market after manufacturers looking to components industry, which exempts lead
July 2006 must pass RoHS compliance. make the switch, there in glass or ceramics as stated below:
The substances banned under RoHS “Electrical and electronic components
include lead (Pb), mercury (Hg), cad-
are options for general- containing lead in a glass or ceramic other
mium (Cd), hexavalent chromium (Cr6), purpose types, but finding than dielectric ceramic in capacitors, e.g.,
polybrominated biphenyls (PBB), poly- stock on any of them will piezo electronic devices, or in a glass or
brominated diphenyl ethers (PBDE), ceramic matrix compound.”
and four different phthalates (DEHP,
be difficult. It’s important to understand exemp-
BBP, BBP, DIBP). The restricted mate- tions and their effective duration. Indus-
rials are hazardous to the environment, the limits don’t apply to the weight of the try regularly applies for the renewal of
pollute landfills, and are dangerous in finished product, or even to a component, exemptions or for additional applications
terms of occupational exposure during but to any single material that could (theo- to be exempted from the Directive’s
manufacturing and recycling. Exceptions retically) be separated mechanically—for requirements.
are the maximum permitted concentra- example, the sheath on a cable or the tin- Each request must be evaluated, and
tions in non-exempt products be 0.1% or ning on a component lead. when appropriate, an exemption is grant-
1000 ppm (except for cadmium, which is ed. Historically, lead-based exemptions
limited to 0.01% or 100 ppm) by weight. RoHS Exemption 7c-1 have been extended, but it’s never a guar-
The restrictions are on each homoge- The RoHS Directive allows for exemp- antee and staying vigilant on the RoHS
neous material in the product. That means tions from its restrictions, under certain site is critical.
GO TO [Link] 15
RoHS Resistor Regulations
RoHS Today
The EU is expected to take the industry recommendations
and extend this exemption for lead containing glass for three
more years from the original expiration date in 2021. In the
past, lead has been an essential element in the dielectric glass
used on nearly all thick-film chip resistors, which comprise the
bulk of the resistors used globally in all markets.
Lead in the dielectric glass is critical to stabilize the laser
calibration trim. It’s worth noting that the lead in this glass
isn’t free lead; it’s chemically bound to the thick-film dielectric
Product Safety Test Equipment material itself. Therefore, the potential for lead contamination
due to the lead content in this material is highly questionable.
ED&D, a world leader in Product Safety Test Equipment However, the worldwide electronics industry has committed
to removing lead from all components and materials used in
manufacturing, offers a full line of equipment for meeting various
manufacturing regardless of the true potential risk in each indi-
UL, IEC, CSA, CE, ASTM, MIL, and other standards. Product line vidual usage case.
covers categories such as hipot, leakage current, ground, force,
Lead-Free Thick-Film Chip Resistor Evolution
impact, burn, temperature, access, ingress (IP code), cord flex,
Some manufacturers have had fully RoHS-compliant chip
voltage, power, plastics, and others. resistors for many years. Some early designs simply removed the
lead-containing dielectric layer completely. Still, these designs
were never successful as they had substantial instability with
ED&D respect to voltage, parasitic capacitance and inductance, and
1-800-806-6236 • [Link] pulse performance.
Later designs utilized more expensive dielectrics or may
have required multiple dielectric layers to be applied prior to
calibration trim. Cost for these early fully compliant series was
typically 5X to 10X the cost of the equivalent general-purpose
chip resistor.
GO TO [Link] 17
Industry Trends
JAMES MORRA | Senior Editor Credit: Ayar Labs
to Shine?
GlobalFoundries has the
backing of Ayar Labs,
Broadcom, Cisco, Marvell,
and NVIDIA.
G
lobalFoundries believes The executive leading this effort is photonics,” said Yu. “But it has been in
there is a bright future Anthony Yu, vice president in its Wired the lab for a long time, and people have
for chips that harvest the and Computing business unit. While it doubted it.”
potential of photons, the could take years for silicon photonics to
building blocks of light, instead of elec- make a serious dent in the data center, he A Long Time Coming
trons to propel data faster at a fraction of said, GF is hoping to get a foot in the door Tech giants have used the power of pho-
the power and cost. with companies betting on the technology tons to send data between geographically
To get there, the U.S.-based foundry to power up artificial intelligence and even distant data centers over fiber optics and
giant is banking on its second-generation quantum computers. even undersea cables for decades. But they
silicon-photonics platform, called GF GlobalFoundries is hoping to hit it are also increasingly using light to move
Fotonix. It has landed design wins with big with GF Fotonix following its IPO data within colossal data centers, haul-
leaders in server networking chips such as last year. It’s pointing to early wins with ing it between tens of thousands of server
Broadcom, Cisco, Marvell, and NVIDIA, companies that plan to use the platform racks. To do so, they are utilizing optical
as well as startups Ayar Labs, Lightmatter, as a sign that silicon photonics is ready networking modules that can be plugged
PsiQuantum, and Ranovus to make chips for mass deployment. directly into switches to convert light into
that move data at the speed of light. Yu said GF Fotonix will open the door electricity and vice versa.
The contract chipmaker is doubling to the next generation of silicon photonics Shorter distances between servers and
down on silicon photonics after falling called co-packaged optics, which prom- various chips inside them are still spanned
behind more generally in the chip sector ise power and cost savings when used in with electrical interconnects that move
when it stepped out of the race with Intel, switch chips that call the shots in data data via copper wires. “The data center
Samsung, and TSMC to make the most centers. Even chip-to-chip interconnects is the foothold for silicon photonics right
advanced processors. will have to use silicon photonics to limit now,” said Yu.
GlobalFoundries has pivoted, with the share of the processor’s power budget Today, moving data at the speed of light
a new focus on feature-rich chips for wasted on I/O. Yu noted some customers means using specialty materials. These
everything from smartphones to cars that want to use GF Fotonix to create chiplets include indium phosphide (InP), the gold
are based on mature technology nodes. that fit the bill. standard in lasers and other technolo-
Business is booming. But it believes sili- “We wanted to announce that silicon gies that can propel photons over opti-
con photonics is its ticket back to the photonics has arrived, and that may sound cal fibers, and silicon germanium (SiGe),
leading edge. strange given all the virtues of silicon which is widely used in the high-speed
GO TO [Link] 19
Silicon Photonics
state-of-the-art in silicon photonics to “The principal feature we have that ously manufactured onto separate chips
solve bottlenecks in system bandwidth, no one else can touch is that we are a that then had to be bundled together in
power, and heat dissipation. completely monolithic process, mean- a package, noted Yu.
The company said GF Fotonix stands ing that we can basically put together a Moving to a monolithic architecture has
out as a monolithic platform that unites photonics system-on-a-chip (SoC),” Yu many pros. The company said GF Fotonix
all of the technology’s building blocks for told Electronic Design. can deliver data rates of up to half a terabit
the first time, including 300-mm photon- All major components, including the per second (Tb/s) over a single fiber, the
ics features and 300-GHz RF-CMOS on passive and active photonics, radio fre- fastest data rate of any foundry offering.
a silicon wafer. quency (RF), and CMOS, were previ- That will allow for optical chiplets run-
ning at 1.6 to 3.2 Tb/s, offering faster data
transmission plus better power efficiency
and signal integrity. The platform also
supports 2.5D packaging technology to
glue chiplets together.
Yu said GF Fotonix is based on 45-nm
CMOS technology, a step up from 90
nm in its first-generation node released
in 2016. Customers can get access to its
Process Design Kit (PDK) to start design-
ing chips for GF Fotonix.
GlobalFoundries also pointed out the
high level of integration in GF Fotonix,
which opens the door for customers to
pack more functions into the same silicon-
photonics IC and reduce bill-of-materials
(BOM) costs.
GO TO [Link] 21
Q&A
WILLIAM G. WONG | Senior Content Director
Why is FIB circuit editing important Internally, the ability to rapidly pro- How are advances in circuit-editing
for semiconductor device development? totype and deliver functional devices technology helping semiconductor
For IC developers, FIB circuit editing supports the efforts of the software and manufacturers overcome some of the
enables debugging and validating fixes, firmware development; testing, validation, current challenges associated with FIB
exploring design optimization changes, and qualification; manufacturing process; circuit editing?
duplicating and scaling pre-production and sales teams. This allows them to move As semiconductors advance, circuit-
parts, and prototyping new devices projects forward and avoid schedule delays. edit solutions are advancing as well to
without committing to the expense and Externally, functional prototypes can meet the market’s needs. For example,
lengthy delay of a mask spin. For many, support ecosystem enablement for key as semiconductor manufacturers move
circuit editing provides real tangible ben- technologies and end-customer’s design- to gate-all-around (GAA) FET architec-
efits that are quantified in cost savings, in and platform validation efforts. This tures and 3D semiconductor packaging,
productivity, and time-to-market. helps fellow travelers hit their milestones new challenges have been encountered
In terms of cost savings, the ability to and intercept market opportunities. that require advances in circuit-edit tools.
rapidly prototype provides the ability to To expand on this, GAAs feature a more
eliminate unnecessary wafer costs and Logic architectures have evolved and complicated architecture that separates
schedule delays. With a full set of masks increasingly become more complex. the transistor blocks, the interconnects,
costing millions of dollars, the financial What are some common design and and power distribution. The GAA also
savings provided by circuit editing can manufacturing challenges? includes wiring layers above the transis-
be substantial. Each generation of architecture and tors, power rails below, and higher tran-
fabrication process node advancement sistor densities.
There’s lots of pressure on the semicon- brings new challenges for semiconductor With transistor layers, interconnects,
ductor industry right now. How does designers and circuit edit, as design and and power distribution stacked on top of
FIB circuit editing accelerate the time- integration complexity increases. each other, a 3D high-aspect ratio struc-
to-market for a chip? For example, the introduction of Fin- ture is created, making it more challeng-
From a time-to-market perspective, FETs in 2011 on 22-nm processor nodes ing to access the active area at depth for
the ability to quickly prototype enables with new architectural structures, multi- circuit editing. With the higher number
internal and external development teams, patterning, and unique thermal and reli- of transistors in a given area, this makes
or partners, to continue product and plat- ability behaviors brought a fundamental it easier to damage them.
form development without waiting six to change to circuit editing. Where point- As a result, GAA circuit editing requires
eight weeks for wafer-processing time to to-point wiring changes were scalable on a higher degree of precision and higher
get new samples. planar FETs, the thinner, dielectric layer in level of control over the rate of the process.
GO TO [Link] 23
Circuit Editing
Thus, there’s a need for circuit-edit tools remove very small amounts of material instruments, these are areas we will con-
with lower landing energies and beam in a controlled manner. tinue to focus on to meet the semiconduc-
currents than what existed up until today. These characteristics make a circuit- tor market’s needs.
Where many of today’s circuit-edit edit solution attractive for other applica-
F
solutions operate at 1.2 pA, state-of- tions, such as deposition of semiconduc-
the-art circuit-edit solutions, such as the tors containing beam-sensitive transistors
or circuit-edit
new Thermo Scientific Centrios HX, can or materials, or for preparation of a device practitioners,
operate at 0.33 pA. This lower landing for failure analysis investigation. it’s a very exciting
energy and lower beam current reduces
damage to sensitive circuits and allows What do you predict is next for the
time and we expect the
the operator to remove very thin layers industry regarding circuit editing? circuit-edit function
with surgical precision. Going forward, many of the challenges will continue to grow in
encountered by IC designers will be simi-
Aside from semiconductor device devel- lar in nature to those that occurred with
strategic value.
opment, are there any other important previous inflection points. For instance,
applications where FIB circuit editing when semiconductors moved from planar For circuit-edit practitioners, it’s a
can be used? to FinFETs, this created a need for circuit- very exciting time and we expect the
When people hear the term “FIB circuit edit tool improvements. circuit-edit function will continue to
edit,” they tend to focus on the circuit-edit From a circuit-edit instrument perspec- grow in strategic value. As devices and
capabilities and don’t consider the FIB’s tive, as semiconductors evolve again, the manufacturing processes become more
capabilities to go beyond. For example, device complexity places a greater pre- complex with more steps, the probabil-
with an advanced circuit-edit solution, mium on accurate ion-beam positioning, ity of functional defects becomes higher.
the user has the sharpest scalpel in their and the ability to make precise, delicate This makes circuit edit and the ability to
toolbox with the ability to simultane- cuts to access and service regions of inter- deliver a functional device very valuable
ously capture high-resolution images and est. As a leader in providing circuit-edit to an organization.
Visit: [Link]
$59.00
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FOCUS ON:
BOB PEASE
ON ANALOG VOL. 1
A compendium of technical articles
from legendary Electronic Design
engineer Bob Pease
LIBRARY
A compendium of articles from Electronic Design
FOCUS ON
PATH TO SYSTEMS
Drea
mstim
e_Kin
ek00
_
2205
8973
6
Essentials for Effective Protection
Against Overvoltage Events
While there’s no one-size-fits-all circuit protection solution, robust overvoltage
protection is a necessity in virtually any application that connects to a power line.
This article explores how to pinpoint the right solution based on app requirements.
P
otentially damaging electri- threaten harm to users through electrical Specifying circuit protection compo-
cal overvoltage threats are an shock or cause a fire. nents is a bit like buying insurance. You
everyday occurrence in today’s To address this wide range of threats, need adequate coverage to prevent dam-
electrical and electronic world. an equally wide range of circuit protec- age, but no one wants to overpay for insur-
Their intensity ranges from very light tion technologies is available. Currently ance they will likely never need.
electrostatic-discharge (ESD) events to available components span from small, Because of the broad selection of cir-
very intense lightning-strike-induced fast PCB-mounted components to large, cuit protection technologies and com-
surges on data lines and power lines. rugged wall-mounted devices. Some of ponents available, it’s helpful first to
These events have the potential to lock up these devices are binary in nature—they categorize the action that an overvoltage
microprocessors, damage sensors, cripple switch on or off. Others are more pro- protection component takes to mitigate
computer communications ports, cause portional or linear in their response to damage. Overvoltage protection devices
severe damage to equipment, and even events. are placed across the line being protected.
Voltage Clamps
Voltage clamps also exhibit very
high resistance at voltages below their
“threshold” voltage (Fig. 2). Once the
4. Shown is the circuit arrangement between the TVS diode and the
Bourns TBU HSP device.
GO TO [Link] 31
Design Solution
JOHN STEVENS | Director of Business Development, Navitas Semiconductor
Dreamstime | Krwphotographic
112757917
Current Sensing:
Past, Present, and Future
While measuring voltage is often a simple task, measuring current is usually not so
straightforward. This article demonstrates a new, highly integrated, “lossless,” and
localized approach to current sensing that deals with many of the challenges.
F
or any electrical control system, protection (like short-circuit overcurrent ing the relationship of voltage = current
input signals of both voltage and protection), and data-logging purposes. × resistance, (V = I × R), and assuming a
current are critical for the sys- stable, or linear, resistance.
tem to operate according to the Shunt Resistors This popular method is simple and
intended design and in a safe manner. One of the simplest methods for mea- accurate. It can be used for dc or ac current
In power supplies and motor drives, for suring current is to add a shunt series measurements and is flexible for a variety
example, current is measured for control resistor into the current path of interest, of applications. While not intrinsically iso-
(like peak-current mode or average-cur- and then measure the voltage across it as lated, some vendors offer isolated ampli-
rent-mode control in power converters), a representation of that current—know- fiers or isolated ADCs for this approach.
GO TO [Link] 33
Current Sensing
Anisotropic Magnetoresistive been able to achieve power densities and power elements of interest. Localized
(AMR) Sensing even 3X higher than best-in-class previ- control and response time allows this
The AMR IC is capable of sensing both ous solutions. But the efforts to extract all method to be fast and effective, while also
ac and dc signals and offering a high- of the capability out of GaN continued, minimizing corruption of the control sig-
bandwidth solution up to 1.5 MHz, with and in late 2021, GaNSense technology nals from system noise, long traces, etc.,
an isolated output. It operates by having offering further integration and expanded compared to other methods. Therefore, it
the current flow into the device through features was released. becomes possible to use this method not
a low-resistance “U-bend” in the lead- In its simplest form, GaNSense is loss- only for overcurrent failsafe and short-
frame, where it generates either a forward less current-sensing in-circuit, removing circuit protection, but also cycle-by-cycle
or reverse magnetic field that’s sensed by the shunt current-sense resistor and its current limit and current-mode control
two differential current sensors. associated headaches (Fig. 3). It improves and regulation.
This approach is attractive in that it’s the overall efficiency of the system with Such a self-governing power block
fairly compact, resistant to external fields lower total series resistance, while also may indeed represent the future of
and noise, and has low offset error while increasing robustness with fast, internal, power-stage sensing and protection,
also responding very quickly (<300 ns). 30- to 100-ns short-circuit protection. enabling higher reliability, pushing
Thus, it can be used in high-frequency This approach is “localized” in that it’s the limits of performance, and freeing
control applications such as power sensed and acted on locally to the current the main system controller to focus on
supplies and motor drives using wide-
bandgap semiconductors such as gallium
nitride (GaN) and silicon carbide (SiC). 4. Shown is a simplified diagram of a
current-sense (CS) current-mirror block
The Future: Introducing in GaNSense technology.
“GaNSense” Technology
With the continued push for higher
efficiency, GaN-based power converters
have become more popular in the market.
In addition, with high levels of integra-
tion used in monolithic GaN power ICs,
power converters could be pushed to
higher frequency with a minimal num-
ber of external components, allowing for
much smaller systems.
Groundbreaking products such as the
latest fast mobile-phone chargers have
Summary
In motor drives and power supplies, volt-
age and current will continue to be signals
that need to be monitored and measured
for accurate and reliable real-time control,
protection, and data logging. With a variety
of applications and requirements comes
multiple current-sensing approaches to
meet the design goals in the most cost-
effective and size-efficient manner.
A technology and approach has been
discussed here with the advent of near-
ideal, lossless “GaNSense” current sens-
ing fully integrated with the power device
that’s fast, accurate, and can serve the criti-
cal functions of both control and protec-
tion with effectively zero size and cost
impact. While not an exhaustive study,
5. Here, GaNSense technology is leveraged in a some of the most common methods used
real power supply. in industry today have been discussed and
are summarized in the table below.
GO TO [Link] 35
Then and Now
WILLIAM G. WONG | Senior Content Director
Dreamstime | Janybaby 878202
A
lot has happened over the past 70 years in the Rise of the CRTs
electronic and display space. Electronic Design We’ll skip past the individual status lights found on early com-
has been covering the technologies and continues puters to the cathode ray tubes (CRTs), which became ubiquitous
to present the latest that are significantly more with the rise of the television. CRTs were driven by custom control-
powerful than those of the past. In fact, graphics processing lers that usually processed signals based on analog standards like
has exceeded what conventional CPUs can do. those from the National Television System Committee (NTSC).
Displays and printed output have been a way to get informa- The CRT was versatile in that it supported vector and raster
tion that’s been fiddled with by a computer into a form that images (Fig. 1). Actually, the raster image is nothing more than
we poor humans can understand. Printers are still around and a fixed format vector image. The difference is that the encoding
hard copy remains a necessity, but video displays dominate the for a raster image maps to the regular movement of the electron
human machine interface (HMI) these days. It shows up in beam, while a vector display moves the beam based on positions
smartphones, HDTVs, and nav systems in cars. Underlying provided by the display controller. An analog oscilloscope is an
these systems are display processors and typically more robust example of a vector display designed to show analog signals
graphics processing units (GPUs). versus a time frame.
GO TO [Link] 37
Graphics Processing
necessarily as fast or as efficient as a GPU optimized for a executed on the GPU. Data and kernels were copied to the
particular application. GPU’s memory and the resulting data was copied back to the
The industry has seen significant consolidation in the GPU CPU’s memory.
space with AMD, Intel, and NVIDIA now dominating the space. The next step was having the GPU move data around, finally
AMD and NVIDIA sell chips that third parties can incorporate unifying the CPU and GPU space, which put the GPU on the
into their products. Some wind up in embedded systems while same level as a CPU. A CPU is normally required within a
others target consumers. They all sell their own brands as well. system with one or more GPUs. However, in many instances,
the CPU simply handles the initial boot sequence and acts as
GPGPUs Add Computational Chores a traffic cop to manage the overall system. GPUs often deal
Initially, GPUs were an output-only device. They were pro- directly with peripherals and storage.
grammable to a degree and typically connected to a display such One reason for unifying the environment is the dominance
as a CRT, projector, or flat panel. Unfortunately, GPUs started of PCI Express (PCIe) and the standards built on top of it, such
out as closed/proprietary systems that were only accessible via as Non-Volatile Memory Express (NVMe) storage and RDMA
drivers provided by the chip vendors. Nonetheless, engineers over Converted Ethernet (RoCE).
and programmers eyed the parallel programming potential that
often exceeded CPU performance. 2D, 3D, and Ray Tracing
Eventually general-purpose GPU (GPGPU) computing 3D displays are one thing, but these days 2D displays still
became available. Standards like OpenCL and NVIDIA’s propri- dominate this space. Mapping 3D environments to 2D displays
etary CUDA make these platforms suitable for general processing is one of the major chores performed by GPUs, driven greatly
chores. Programming was different from a CPU, but languages by 3D gaming.
like C were augmented to work with the new, exposed hardware. Initially, 3D to 2D mapping was done without taking ray
Part of the challenge was mapping programs to the hardware tracing into account because of the overhead required. Graphic
that started out supporting gaming and graphical displays. Map- artists handle textures and lighting explicitly to mimic how a
ping 3D environments onto a 2D presentation were part of the scene would be rendered in the real world.
driving factors for developing the single-instruction, multiple- Explicit transformations done by artists and designers provide
data (SIMD) and single-instruction, multiple-thread (SIMT) the fastest but least realistic way of turning a 3D gaming world
architectures. The surge of this type of programming is relatively into a 2D presentation. Ray casting is a methodology that’s fast
recent, starting about 2006. and provides more realistic rendering based on a 3D model,
Since then, the scope and chip architectures have changed while ray tracing matches a real-world scenario only limited by
radically, especially with the incorporation of machine-learning the resolution of the system. Check out Jon Peddie’s “What’s the
(ML) and artificial-intelligence (AI) acceleration. The GPG- Difference Between Ray Tracing, Ray Casting, and Ray Charles?”
PUs were ideal for handling AI/ML models compared to CPUs, article on [Link] if you get a chance.
although the GPGPUs are being bested by AI/ML accelerators Ray-tracing hardware, now available from a number of sourc-
optimized for specific tasks. Likewise, CPUs and GPGPUs now es, is found in very-high-end GPGPUs. This includes embedded
implement AI/ML acceleration and AI/ML-optimized opcodes GPGPUs like those intended for mobile devices (e.g., smart-
along with data handling, making them even better for these phones). These provide amazingly realistic and beautiful images.
kinds of applications. Imagination Technologies identified five levels of ray-tracing
Originally, GPGPUs were a compute island with their own support from software through low-level hardware support to full
memory and programming elements (Fig. 3). The original hardware ray-tracing support with a scene hierarchy generator.
split-memory approach was one reason why GPGPU parallel- What makes the ray-tracing support interesting these days
programming object code was delivered in “kernels” that were is that it’s being done in real-time. Ray-tracing support initially
used in movie computer generated imagery (CGI) special effects
often required days and a supercomputer of that time to render
part of a video clip. This is now being accomplished on a single
GPGPU card at 4K resolution in real-time and will eventually
be done on a mobile device.
Not all graphical display applications require this level of
performance or sophistication, but computer image and video
content continue to dazzle users. Expect the future to make
things even more interesting.
3. GPGPUs have moved from a split-memory architecture (left) to a To view more images associated with this article, go to the
unified memory architecture (right). Credit: NVIDIA online version at [Link].
out “grooves” in the die to support pas- the form of a chiplet that can be pack-
sive attachment of fiber optics—up to 16 aged into everything from CPUs to GPUs
fibers in the case of co-packaged optics— to supply up to 1,000X more bandwidth
increasing bandwidth density. than electrical I/O—using one-tenth of
the power.
AI at Speed of Light CEO Charles Wuischpard said it part-
As the decline of Moore’s Law takes nered closely with GlobalFoundries to
a toll on the technology industry, other integrate its unique requirements into
companies are trying to push silicon pho- GF Fotonix. Ayar Labs was also the first
tonics even deeper into data centers. company to build a prototype on top of
Today, data dashes through optical fiber the platform.
in data centers before it slows to a crawl at GF Fotonix sets the stage for the com-
copper interconnects. These bottlenecks pany, which has also partnered with HPE
occur at copper pins and wires on circuit to design a future generation of its Sling- Xanadu, a startup relying on silicon photon-
boards. As a result, major semiconductor shot interconnect for high-performance ics for quantum computing, has also backed
firms and startups are setting their sights computing, to supply thousands of units GF Fotonix. Credit: Xanadu
on using silicon photonics to transfer data of its chiplet this year.
over shorter distances, such as between impossible today. But prospects for Q1
CPUs, GPUs, and other computer chips in If You Build It, They Will Come and other systems to change the world
a server or even on a circuit board (PCB). Yu said the collaboration with its cur- remains years out.
NVIDIA indicated that it’s designing rent roster of customers helped it to create To lend a helping hand to current and
high-bandwidth, low-latency, power- a silicon-photonics platform for everyone future customers, GlobalFoundries is
efficient optical interconnects based on else to use, even in areas such as telecom, building out a more vibrant ecosystem
GF Fotonix into some of its “leading-edge” aerospace, defense, and automotive. of software tools, support, and services
data-center systems to handle increasingly Lightmatter, a startup using silicon around the GF Fotonix platform. Ansys,
heavy AI workloads. photonics to accelerate AI workloads in Cadence Design Systems, and Synopsys
Yu said one advantage of GF Fotonix is data centers, as well as improve energy are offering suites of electronic design
that the monolithic architecture reduces efficiency, also plans to use the GF Foto- tools that support photonics-based chips
the rate that errors occur in data trans- nix platform for its first accelerator chip and chiplets.
mission, lowering latency by a factor of due out in 2022. Said Lightmatter CEO “I don’t want to say it’s one-size-fits-all,”
10, which in turn translates to higher Nicholas Harris, “Together we’re changing said Yu. “It’s not that simple. But with one
throughput for AI workloads. the way the world thinks about photonics.” foundry platform with differentiated fea-
To make things easier for itself, NVID- PsiQuantum is building out a quantum tures and using unique materials, you can
IA has partnered with Ayar Labs, a startup computer called Q1 with help from Glo- open up photonics to a variety of markets.”
designing optical interconnects that can balFoundries. Photons are used to solve GlobalFoundries plans to complete
be bundled into various processors and problems many millions of times faster, qualification of GF Fotonix to support a
accelerators. The interconnects come in and even carry out computations that are production ramp-up by 2024.
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GO TO [Link] 39
Lab Bench
WILLIAM G. WONG | Senior Content Director
Mini-ITX Motherboard
Packs Two AI Accelerator Chips
Flex Logix’s InferX Hawk motherboard is designed for applications such as machine-
learning-based video systems that handle tasks like object detection.
I
’m looking forward to checking out
the InferX Hawk from Flex Logix (see
figure). The Mini-ITX motherboard
has a quad-core, AMD Zen+ host
processor with a Radeon Vega GPU and
video codec accelerator. However, the
machine-learning (ML) heavy lifting is
done by a pair of Flex Logix InferX X1
artificial-intelligence (AI) accelerators
that can be used individually or in tan-
dem. It brings ML/AI acceleration to the
edge in a complete package.
The InferX X1 chip utilizes multiple
single-dimensional Tensor processors that
can be configured on the fly. It supports
a high-precision Winograd acceleration
option that increases system utilization
The InferX Hawk sports a quad-core, AMD Zen+ processor with a Radeon Vega GPU
and overall efficiency. The reconfigura-
to support twin InferX X1 machine-learning accelerator chips. Credit: Flex Logix
tion feature allows for support of two- and
three-dimensional tensors.
T
The chip also incorporates embedded
FPGA (eFPGA) logic, opening the door he InferX X1 chip utilizes multiple single-
to further customization. With the on-
chip memory and reconfigurable fabric,
dimensional Tensor processors that can be
intermediate results can be kept locally configured on the fly.
instead of bringing off-chip memory into
play. The system is able to handle stan- eration, the AMD processor was paired ports, plus five USB ports for USB 2.0,
dard conv2d models as well as depth-wise with the two InferX X1 chips to balance 3.1, and 3.2 (Type-C) connections. The
conv2d models. Each chip can manage the overall system throughput and take system requires from 25 to 40 W of power
multiple models depending on their size, advantage of AMD’s video-processing depending on the workload.
or the two chips may be combined to deal hardware capabilities. The system is supported by Flex Logix’s
with one large model. The motherboard supports up to EasyVision, which includes pretrained
Almost any ML model works with the 32 GB of DDR4 SO-DIMM memory. and configured models for video applica-
InferX X1 chips, but video processing is There’s an M.2 M key and an M.2 E tions such as face-mask and license-plate
an area where it excels. This includes key socket—the former targets NVMe identification. In addition, it can check
applications such as object recognition SSDs, while the latter supports smaller for PCB defects and perform battery
within a video stream. Video streams are peripherals such as a wireless adapter. inspection. The EasyVision models work
normally provided via USB or gigabit The backplane features a pair of Display- with the InferX Model Development Kit
Ethernet (GbE). Taking this into consid- Port sockets, two GbE sockets, two serial (MDK) and the Run Time Kit (RTK).
Loss Leaders
Coilcraft’s XGL Family of molded power much cooler than other components.
inductors is available in a wide range of All XGL Family inductors are qualified
inductance values (from 82 nH to 47.0 μH) to AEC-Q200 Grade 1 standards (with a
and current ratings up to 43 Amps. With up maximum part temperature of 165°C) and
to 60% lower DCR than previous-generation have no thermal aging issues, making them
products, they are the most efficient power ideal for automotive and other harsh
inductors available today! environment applications.
Their ultra-low DCR and higher Irms Download the datasheets and request free
also allow XGL Family inductors to operate samples at [Link]/XGL.
[Link]