Korea Winter Public Conference ORTC 2011 ITRS

2011 Renewal ITRS ORTC Technology Trend Pre-Summary Unchanged for 2010/11 MPU contacted M1 1) 2-year cycle trend through 2013; then 3-year trend to 2026 2) 60f2 SRAM 6t cell Design Factor 3) 175f2 Logic Gate 4t Design Factor 4) Ongoing - evaluate alignment of nodes with latest M1 industry status and also High Performance/Low Power timing needs 2) Unchanged for 2010/11 Tables: MPU Functions/Chip and Chip 1)

Size Models
Design TWG Model for Chip Size and Density Model trends tied to technology cycle timing trends and cell design factors 2) ORTC line item OverHead (OH) area model, includes non-active area 3) Updated for 2010/11 Tables: MPU GLpr, GLph trends 1)

4)

5)

smoothed by PIDS modeling; but close to previous targets Updated for 2010/11 Tables: Vdd Low operating and standby line items from PIDS model track smoothed gate length changes Added in 2011 Table ORTC-6 Battery Energy Storage (Watt-hours) Line Item from iNEMI Roadmap
2

2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

Updated in ORTC 2011 Tables - DRAM contacted M1: 1) 1-year pull-in of M1 and bits/chip trends; 2) no Flattening of DRAM M1 as with Flash Poly** 3) 4f2 push out [to 2013]; 7) Updated in ORTC 2011 Tables - Flash Un-contacted Poly: 1) 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm; 2) and 3bits/cell extended to 2018; 4bits/cell delay to 2022 8) Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model: 1) 3-year generation Moores Law bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 2x/2.5yrs) 9) Updated in ORTC 2011 Tables - Flash Bits/Chip and Chip Size 6)

Model:
1) 2) 3-year generation Moores Law bits/chip doubling cycle target (after 1-yr acceleration; then flat @ 1-2Tbits; keep chip size <160mm2); New 3D layers Models vs. relaxed half-pitch tradeoffs are now included in the 2011 Renewal for maximum bits per chip
3

2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

10) Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask Counts
MPU, DRAM,

1) Flash Survey inputs Updated

2) Also IC Knowledge (ICK) model contribution to extend mask levels range

11) Unchanged for 2011 - IRC 450mm Position:

1)
1) 2) 3)
2)
1)

Timing Status
Consortia work underway IDM and Foundry Pilot lines: 2013-14; Production: 2015-16 SEMATECH/ISMI making good progress on 450mm program activities to meet the ITRS Timing
Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers schedules 450mm increasing silicon demand is needed from consortium demonstrations to support development

2) 3)

3) 4)

5)

Europe momentum building - EEMI status reviewed with IRC in Potsdam FI TWG will extend 300mm wafer generation in parallel line item header with 450mm; 1) Including Technology upgrade assumptions through end of roadmap 2) Assuming compatibility of 300mm productivity extensions into the 450mm generation; Utilizing a new ITRS-based ICK Strategic commercial model , SEMATECH has developed 300mm and 450mm 2009-2024 Range Scenarios for silicon and equipment demand New Moores Law and More Graphic update included in 2011 ITRS Executive Summary MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting New MEMS TWG and Chapter added to 2011 ITRS 4

12) Updated in 2011 - More than Moore white paper online at www.itrs.net
1) 2) 3)

2011 Renewal ITRS ORTC Technology Trend Summary (cont.) Technology Pacing Cross-TWG Study Group (CTSG) work preparation for 2012 Update: IRC Equivalent Scaling Graphic Update
Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility materials pathway Proposals for pull-in placement of MuGFET [2012 Update work] and III/V Ge Timing [consider in 2013 ITRS work] (one IDM or Foundry company may lead technology production ramp)

PIDS and FEP Memory Survey Proposal Updates

Additional acceleration will be monitored

FEP and Design and System Drivers Logic Monitor

Monitor MPU and Leading Edge Logic technology trends

A&P/Design Power Model

Possible proposals for Power Dissipation "hot spot" model rather than chip area basis

PIDS/Design Max On-chip Frequency vs Intrinsic Modeling

Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010 plus 4% CAGR trend) TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from unchanged 2011 13% trend] PIDS Updates include MASTAR static modeling near-term and TCAD dynamic long-term modeling Also equivalent scaling tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling

YE Defect Density Modeling

New ORTC Defect Density model work moved to 2012 Update due to loss of modeling resources 5

Figure 4

The Concept of Moores Law and More

More than Moore: Diversification
HV Power Sensors Actuators

Analog/RF

Passives

Biochips

Baseline CMOS: CPU, Memory, Logic

More Moore: Miniaturization

130nm

Interacting with people and environment Non-digital content System-in-package (SiP) Information Processing

90nm
65nm 45nm 32nm 22nm 16 nm . . . V Beyond CMOS

Digital content System-on-chip (SoC)

Source: 2011 ITRS - Exec. Summary Fig. 4

Exec. Summary - Figure 1 Definition of Half-Pitch

More Poly Dense Lines added in 2010 ITRS Update

[Note: The ITRS does not utilize any single-product node designation reference; Flash Poly and DRAM M1 half-pitch are still Lithography drivers; however, other product technology trends may be drivers on individual TWG tables]

FLASH Poly Silicon Pitch = Flash Poly Pitch/2 Poly Pitch

DRAM Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 Pitch = MPU/ASIC M1 Pitch/2 Metal Pitch

32-64 Lines Typical flash Un-contacted Poly

Source: 2011 ITRS - Exec. Summary Fig. 1

Typical DRAM/MPU/ASIC Metal Bit Line

Figure 2a Production Ramp-up Model and Technology/Cycle Timing

- (within an established wafer generation*) - *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also - Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production Ramp Curves Proposal For 2012 Update Note: Fewer leading IDM Companies Requires Adaption of Definition To allow one IDM Company Or a Foundry Representing Many Fabless Companies To Lead a Technology Production Ramp Timing
Additional Lead-time: ERD/ERM Research and PIDS Transfer

Development

Production

200K

Volume (Wafers/Month)

20K

2K

Alpha Tool

Beta Tool

Production Tool

First Conf. Papers

Proposal: First 1-2 Companies Reaching Combined Production (work in Progress)

12 24

200 20

-24

-12

Source: 2009 ITRS - Exec. Summary Fig. 2a

0 Months

Work in Progress - Do Not Publish

Figure 2b A Typical Technology Production Ramp Curve for ERD/ERM Research and PIDS Transfer timing - including an example for III/V Hi-Mobility Channel Technology Timing Scenario - Acceleration to 2015 Scenario for the 2012 Update work

Research

Development

Production

200K 20K 2K

Transfer to PIDS/FEP
(96-72mo Leadtime) First Tech. Conf. Device Papers Up to ~12yrs Prior to Product

Alpha Beta Product Tool Tool Tool

200

First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product

1st 2 Cos Reach Product

20 2

-96
Hi-m Channel 2011 Example:

-72
2013

-48
2015

-24
Months
2017

0
2019

24
2021 9

Hi-m Channel Proposal - for 2013 ITRS work

Source: 2011 ITRS - Exec. Summary Fig. 2b; plus:

[http://www.eetimes.com/electronics-news/4087596/Intel-s-Garginipushes-III-V-on-silicon-as-2015-transistor-option ]

Volume (Wafers/Month)

2012 ITRS Update* 450mm Production Ramp-up Model

[ 2011 ITRS Executive Summary Fig. 6 - A Typical Wafer Generation Pilot Line and Production Ramp Curve]

Development
<---------------------------------------- Consortium

Demonstration
-------------------------------------------

Production
Manufacturing

Alpha Tool

Beta Tool

Demonstrations focus on 1xnm M1 half-pitch capable tools ------ IDM & Foundry ------ Pilot Lines

Volume

Silicon is supporting development using partially-patterned and processed test wafers

Increasing 450mm Silicon Demand From Demonstrations

Beta Tool

Production Tool

2010

2011

2012

2013

2014

2015

2016

Years
*Note: the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 Update Roadmap guidance; based on SEMATECH guidance

10
Source: 2011 ITRS - Executive Summary Fig. 6

2011 ITRS Figure 11 ORTC Table 1 Graphical Trends Memory Half Pitch [With 2011 Flash 3D Scenario Overlay]
2011 ITRS - Technology Trends
1000

2011 ITRS Flash Pitch (nm) (un-contacted Poly) [2-yr cycle to 2009; then 8-yr cycle to 2020; then 3yr cycle to 2022/8nm; then flat]

100

2011 ITRS DRAM Pitch (nm) (Contacted M1) [2.5-yr cycle to 2008; 45nm pull-in to 2009; then 3-yr cycle to 2026]

Nanometers (1e-9)

PIDS 3D Flash : Looser Poly half-pitch 2016-18/32; Then 2019-21/28; Then 2022-25/24 Then 2025-26/18nm ~5.5-yr Cycle

3D - 8 layers

3D - 128 layers

16nm
10

1 1995

2000

2005

2010

2015

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026

Source: 2011 ITRS - Executive Summary Fig 3

Long-Term 19-26

11

2011 ITRS Figure 4 ORTC Table 1 Graphical Trends Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
2011 ITRS - Technology Trends
1000

2009/10/11 ITRS MPU/ASIC Metal 1 (M1) Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3yr cycle] 2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
100

Nanometers (1e-9)

2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]

16nm
10

1 1995

2000

2005

2010

2015

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026

Source: 2011 ITRS - Executive Summary Fig 4

12

Long-Term 19-26

2011 ITRS Figure 5 Equivalent Scaling Roadmap for Logic (MPU and high performance ASIC) Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic nodes and ITRS trends for comparison); also including proposals for MugFET and III/V Ge acceleration for 2012 ITRS Update work
Metal Metal High k Metal High k

Gate-stack material

High k

2nd generation

nth generation
S

Proposal - for 2013 ITRS work

Channel material

D
Proposals - for 2012 Update work

Si + Stress

High- InGaAs; Ge

Bulk Structure (electrostatic control)

Possible Pull -in

Multi-gate (on bulk or SOI)

Possible Delay

PDSOI
2011 ITWG Table Timing:
2011 ITRS Flash Poly : 2011 ITRS DRAM M1 :

FDSOI
2013

2007 54nm 45nm 68nm 45nm 54nm 47nm 32nm 29nm

2009
45nm 32nm

2010 32nm 22nm 22nm 38nm 35nm 24nm

2012
32nm 16nm 32nm 27nm 31nm 28nm 22nm 20nm

15nm

2016

2015
22nm 11nm 19nm 20nm 15nm

2018
16nm

2019 11nm 8nm 13nm 14nm 12nm

2021

2021
11nm

22-24 8nm 2024 8nm

MPU/hpASIC Node:
2011 ITRS MPU/hpASIC M1 : 2011 ITRS hi-perf GLpr : 2011 ITRS hi-perf GLph :

76nm 65nm 54nm 45nm 47nm 41nm 29nm 27nm

13
Source: 2011 ITRS - Executive Summary Fig 5

1995->2015 Nodes 360-11(10)

2011 ITRS Figure 4 ORTC Table 1 Graphical Trends Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
2009/2010 ITRS Unchanged (except extend to new end period): 2011 ITRS: 2011-2026; also ncludes 2012 Update Equivalent Scaling Proposals

ITRS M1 hp 303-21nm
ITRS GLph 95-99-03-15 360nm-90nm 90nm-45nm 1000 45nm-17nm

2011 ITRS - Technology Trends

Half-Pitch + Design Factor Scaling [6t SRAM = 60f2; 4t Logic = 175f2] Enables Moores Law Functions/ chip

2009/10/11 ITRS MPU/ASIC Metal 1 (M1) Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3yr cycle] 2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
100

Nanometers (1e-9)

ITRS 1999 P. Gargini Equivalent Scaling Concept Strain HK/MG PDSOI

2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]

16nm
FDSOI MuG-FET Equiv. Scaling Tradeoff Hi-u,(tbd) 2011 ITRS: Extend M1; & GLpr; to 2026 on 3-year Cycle

10
Gate Length + Equivalent Scaling = Power & Performance

MugFET from 2015 -> 2011; Proposal for 2012 ITRS Work

Updated Equivalent Scaling Proposal - for 2012 work

Also III/V; Ge from 2019 -> 2015? Proposal for 2013 ITRS Work

1 1995

2000

2005

2010

2015

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026

Source: 2011 ITRS - Executive Summary Fig 4

14

Long-Term 19-26

2011 ORTC Figure 6 Product Function Size Trends

1.00E+04

2011 ITRS - Function Size

2009 DRAM Cell area per bit (1 bits/cell) (um2)
[transistor + capacitor]

2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2) 1.00E+03

2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2) 2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2)

1.00E+02

2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2011 SRAM Cell (6-transistor) Area (um2)

1.00E+01

2011 Logic Gate (4-transistor) Area (um2)

Square Millimeters

1.00E+00

1.00E-01

1.00E-02

1.00E-03

1.00E-04

1.00E-05

1.00E-06 1995

2000

2005

2010

2015

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026

Source: 2011 ITRS - Executive Summary Fig 6

Long-Term 19-26

15

2011 ORTC Figure 6 Product* Function Size Trends; plus

1.00E+04

PIDS NAND Flash Multi-Layer 3D Model

Plus Shallow Dimensional Reduction Rate Trend

2011 ITRS - Function Size

2009 DRAM Cell area per bit (1 bits/cell) (um2)
[transistor + capacitor]

1.00E+03

1.00E+02

MPU/ASIC Alignment Design TWG Actual SRAM [60f2] & Logic Gate [175f2]

2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)

2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2) 2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2) 2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2011 SRAM Cell (6-transistor) Area (um2)

1.00E+01

2011 Logic Gate (4-transistor) Area (um2)

Square Millimeters

1.00E+00

1.00E-01

1.00E-02

1.00E-03

DRAM 4f2 Added WAS:Begin in 2011 IS: Delayed To 2013

2016-2025 32nm-18nm = -6.193% CARR Dimensional = -12.00% CARR Area = 0.8800x/yr 0.5/5.5yrs = 0.3165/9years 3D Equiv. 2016-2025 1 - 128layers 41.674% CARR Area = 0.5833x/yr x0.8800/yr = 0.5133x/year

1.00E-04

1.00E-05

Flash [4f2] 1) 2-yr Cycle Extended to 2010; 2) 3 bits/cell added 2009-2011[and extended to 2020 in the 2011 ITRS]; 3) 4 bits/cell moved from 2012 [to 2021 in the 2011 ITRS]

2016/32nm 0.0039 um2 3D - 8 layers/16 2016/32nm 0.00048 um2

3D - 128 layers/ 25

2025/32nm
0.0030 um2
2030

1.00E-06 1995

2000

2005

2010

2015

2020

2025

Year of Production

2011 ITRS: 2011-2026

2025/18nm 0.000965 um2

Source: 2011 ITRS - Executive Summary Fig 6

Long-Term 19-26

16

Figure 7 2011 ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average Moores Law and Chip Size Trends 4Tbits Possible with PIDS 2009 ITRS - Functions/chip and Chip Size NAND Flash Multi-Layer Flash MLC 3D Model Scenario Option Exceeds 10000.00
Flash ~ 2x/3yrs
1000.00

1Tera-bit

Gigabits (1e9) and Square Millimeters

<160mm2 (18 x 9) 100.00

Flash ~ 2x/1.25yrs
10.00

<30mm2 (8 x 4)

Flash "Hwang's Law" ~ 2x/1yr

DRAM ~ 2x/2.5yrs

2011 ITRS DRAM Functions per chip (Gbits)

2011 ITRS Flash (Gbits) SLC [2-year cycle] 2011 ITRS Functions per chip (Gbits) MLC (2 bits/cell)
2011 ITRS Functions per chip (Gbits) MLC (3 bits/cell) 2011 Functions per chip (Gbits) MLC (4 bits/cell)

1.00

0.10

Average "Moore's Law" = 2x/2yrs

0.01 1995 2000 2005 2010 2015

2011 Flash Chip size at production (mm2)

2011 DRAM Chip size at production (mm2)

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026 Long-Term 19-26

Source: 2011 ITRS - Executive Summary Fig 7

17

Figure 8 2011 ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average Moores Law and Chip Size Trends [unchanged from 2009, except extended to 2026]
2011 ITRS - Functions/chip and Chip Size
10000000
2011 ITRS Cost-Performance MPU Functions per chip at production (Mtransistorst)

Million Transistors (1e6) and Square Millimeters

1000000
2011 ITRS High-Performance MPU Functions per chip at production (Mtransistors)

Average "Moore's Law" = 2x/2yrs MPU = 2x/3yrs

MPU/hpASIC M1 Technology Cycle and MPU Transistors/chip are On 3-year Cycle after 2013 vs. Average 2-year Historical Moores Law 2011 ITRS: Unchanged, but Extend ed Transistors/chip & Chip Size Models to 2026 On 3-year Cycle

100000

2011 Cost-Performance MPU Chip size at production (mm2)

MPU = 2x/2yrs

10000

2011 High-Performance MPU Chip size at production (mm2)

22nm/(38nm M1) MPU Model Generations

1000

<260mm2 <140mm2
100

10 1995

2000

2005

2010

2015

2020

2025

2030

Year of Production

2011 ITRS: 2011-2026 Long-Term 19-26

Source: 2011 ITRS - Executive Summary Fig 8

18

ORTC Table 5 Update: Litho TWG model for Mask Count

MPU survey-based, mask counts peak 2014/(54 masks peak) EUV expected 2015 DRAM referenced to MPU, mask counts peak 2012/(41 masks peak) EUV expected 2013 Flash survey-based, mask counts peak 2012/(43 masks peak) EUV expected 2013 Sidewall image transfer technology IEDM papers should be evaluated Table 5 also includes NEW IC Knowledge (ICK) www.icknowledge.com modeled comparison targeting ITRS 2011 Litho EUV timing; but extended out through 2024 using 2009-10 ITRS (www.itrs.net ) assumptions Limited YE Defect Density modeling resources requires delay of update response to 2012 ITRS Update work

19

Fig 7a - Litho 2011 Survey vs ICK 2011 ITRS-based* Model

[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]

Litho Mask Count by Product Category

80 70 60
450mm 20152016

SEMATECH Survey

50

DRAM
Flash

40
30
Actual < - > Forecast

MPU
EUV timing: MPU in 2015; DRAM & Flash in 2013
20

20
1995 2000 2005 2010 2015 2020 2025

Source: 2011 ITRS - Executive Summary Fig. 7a

Fig. 7b - Litho 2011 Survey vs ICK 2011 ITRS-based* Model (cont.)

[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]

80
Litho Mask Count by Product Category

70

MPU Delay EUV to 2017

450mm 20152016

ICK Strategic Model*

*Based on ITRS 2009-10 editions

60
50 40 30

Flash Charge Trap in 2012; Multi-layer 3D begins 2016

DRAM Flash MPU

EUV timing: MPU in 2015;
Actual < - > Forecast

20

1995

2000

2005

2010

2015

2020

2025

DRAM & Flash EUV in 2013

Source: 2011 ITRS - Executive Summary Fig. 7b

21

Table FreqTopic tbd - 2011 Chip Frequency Model Trend vs.2009/2010 ITRS Frequency
Table ORTC-4 Performance and Packaged Chips Trends
Year of Production

Ghz

2009
5.454 3.462

2010
5.875 3.600

2011
6.329 3.744

2012
6.817 3.894

2013
7.344 4.050

2014
7.911 4.211

2015
8.522 4.380

2016
9.180 4.555

2017
9.889 4.737

2018

2019

2020

2021

2022

2023

2024

2025

2026

Chip Frequency (MHz) WAS On-chip local clock [2] Design On-chip local clock [2] /IS

10.652 11.475 12.361 13.315 14.343 15.451 16.640 4.927 5.124 5.329 5.542 5.764 5.994 6.234 6.483 6.743

ORTC Table 4: Design TWG Model for OnChip Frequency

Lower model starting point 2010/3.6Ghz 4% growth rate through 2026 *Unchanged 2011 ITRS 13% PIDS target model Intrinsic Transistor Frequency Growth; *However, proposal for 2012 ITRS 8% PIDS target model Intrinsic Transistor Growth (work preparation in 2011)
Source: 2011 ITRS - Executive Summary Table tbd

22

Fig 8a - PIDS 2009/11 ITRS CV/I Trends vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
1000
PIDS 2011 ITRS Table: 1/(CV/I) (Ghz) = 11/156 26/1000 @ ~ 13% CAGR

Extended Planar Bulk UTB FDSOI

1/(CV/I )(Ghz)

11/ 313 26/686 @ 5.4% CAGR MugFET Trend

1/(CV/I) (Ghz) ~ PIDS Table 2: CV/I 2009-2011 ITRS Unchanged ~ 13% CAGR PIDS 2012 FDSOI Scenario: 15/294 26/686 @8.0% CAGR

Multiple Gate 2010 ITRS; 2011 ITRS Unchanged

[2012 Proposal: MugFET 4-year Leading Co. pull-in]

Multiple Gate Pull-in Scenario - 2012 ITRS

Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example .1pf); FO 4 (capacitance example .4pf)

100

2000

2015

2020

Year of Production Ramp 2011 ITRS

1.00
PIDS 2011 ITRS Table: CV/I) (ps) = 11/0.64 26/0.10 @ ~ -12% CAGR 11/ 0.319 26/0.146 @ - 4.8% CAGR MugFET Trend [2012 Proposal: MugFET 4-year Leading Co. pull-in] 2011 - 2026 CV/I (ps) ~ ~ -12% CAGR PIDS 2012 FDSOI Scenario: 15/0.340 - 26/0.146 -7.4% CAGR

2030

2005

2010

2025

Extended Planar Bulk UTB FDSOI Multiple Gate 2010 ITRS; 2011 ITRS Unchanged

CV/I (ps)

Multiple Gate Pull-in Scenario - 2012 ITRS

Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example .1pf); FO 4 (capacitance example .4pf)

0.10

2000

2010

2015

2025

Year of Production Ramp

Figure 8a 2012 Update Model Trend versus 2009/2011 ITRS PIDS TWG Transistor Intrinsic Frequency (1/(CV/I)) Performance Trends

2030

2005

2020

23

Source: 2011 ITRS - Executive Summary Fig. 8a

Fig. 8b - ORTC Table 4:On Chip Local Clock Frequency Trend Comparisons to PIDS vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
2009/11 ITRS PIDS/FEP Intrinsic Transistor Frequency 1/(CV/I) at 13% CAGR 2012 Update Scenario: MugFET : 4yr Pull-in 1/(CV/I) to 2011; then 5% CAGR 2012 Update Scenario FDSOI: Beginning 2015 at 8% CAGR 1Thz 2009/11 PIDS/FEP Ring Oscillator Model 101 invertor stages With equivalent Fan-out 4 Capacitance load; Results in Frequency of ~ 1/22 x 1/(CV/I) at ~13% CAGR 2012 Update Scenario: FDSOI at 8% CAGR 2012 Update Scenario: MugFET at 5% CAGR

100
~ 1/22

10

Design Hroom

Intel Actual Co.A Actual

Co.B Actual AMD Actual
Co.C Actual IBM Actual

1
2007 Des TWG Actual History of Average On-Chip 1999 - 2007 1Ghz 4.9Ghz ~22% CAGR

On-Chip Clock Frequency: Performance Improvement tradeoffs between dimensional EOT and Gate Length with Equivalent Scaling, both process-related (ie Strain, FDSOI, MugFET, III/V Ge, etc); and also Including design-related tradeoffs: -Multi-Core Architecture -Memory Architecture -Software Power Management -etc.]
2011 ITRS 2011 - 2026

2005 ITRS (18%) 2007 ITRS (8%) 2011 ITRS (4%)

ORTC Table 4: On-Chip Local Clock Frequency: 2011 Design TWG trend: at 4% CAGR

0.1 1995

2000

2005

2010

2015

2020

2025

Source: ITRS Test TWG compilation, ca 4Q 2010; 2011 ITRS PIDS, Design TWGs Figure 8b Design On-Chip Frequency vs. PIDS Intrinsic Transistor and Ring Oscillator Model Frequency
Source: 2011 ITRS - Executive Summary Fig 8b

24