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# Computer Organization & Architecture Lecture #3 Flip-Flops Edge-Triggered D Flip-Flop The D flip-flop has two inputs data input

t (D) clock input (Ck). A small arrowhead on the flip-flop symbol identifies the clock input. The flip-flop output changes only in response to the clock, not to a change in D. The next state value, Q+, for the D flip-flop is the current value of the D input when the appropriate pulse edge of the clock input is encountered. If the output can change in response to a 0 to 1 transition of the clock input, the flip-flop is triggered on the rising edge (or positive edge) of the clock. If the output can change in response to a 1 to 0 transition of the clock input, the flip-flop is triggered on the falling edge (or negative edge) of the clock. Shown below are two block diagrams for the D flip-flop.

The left one uses the rising-edge of the clock pulse to trigger a state change. The right one uses the falling-edge of the clock pulse to trigger a state change. The inversion bubble on the clock input on the right is used to indicate a falling-edge triggered flip-flop. Shown below is the truth table or the next state table for the D flip-flop.
D 0 0 1 1 Q 0 1 0 1 Q+ 0 0 1 1

Notice that the next state value always follows the D input. Because of this the characteristic equation can be easily derived directly from the truth table. Q+ = D

Shown below is the timing diagram for the D flip-flop. (Falling Edge)

S-R Flip-Flop An S-R flip-flop is similar to an S-R latch in that S = 1 sets the next state value, Q+, to 1 and R = 1 resets the next state value, Q+, to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge. The truth table and the characteristic equation for the S-R flip-flop is the same as that of the S-R latch. Shown below is the block diagram for the S-R flip-flop.

The J-K Flip-Flop The J-K flip-flop is an extended version of the S-R flip-flop. The J-K flip-flop has three inputs J, K, and the clock (CK). The J input corresponds to the S input, and the K input corresponds to the R input. If J = 1 and K = 0, the next state value, Q+, is set to 1 after the active clock edge. If J = 0 and K = 1, the next state value, Q+, is reset to 0 after the active clock edge. If J = 0 and K = 0, the next state value, Q+, equals the present state value, Q. Unlike the S-R flip-flop, J = 1 and K = 1 input values may be applied simultaneously. If Q = 0, the next state value, Q+, is set to 1 after the active clock edge. If Q = 1, the next state value, Q+, will be reset to 0 after the active clock edge.

## Shown below is the block diagram for the J-K flip-flop.

Shown below is the truth table or next state table for the J-K flip-flop.
J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 1 0

KQ\J 00 01 11 10

0 0 1 0 0

1 1 1 0 1

Q+

JQ + KQ

## Shown below is the timing diagram for the J-K flip-flop.

The T Flip-Flop The T flip-flop, also called a toggle flip-flop, is frequently used in building counters. The T flip-flop has two inputs T and the clock (Ck). When T = 1 the flip-flop changes state after the active edge of the clock. If Q = 0, the next state value, Q+, will be set to 1. If Q = 1, the next state value, Q+, will be reset to 0. When T = 0, no state change occurs. Shown below is the block diagram for the T flip-flop.

Shown below is the truth table or next state table for a T flip-flop.
T 0 0 1 1 Q 0 1 0 1 Q+ 0 1 1 0

## Shown below is the timing diagram for the T flip-flop.

Flip-Flops with Additional Inputs Flip-flops often have additional inputs which can be used to set the flip-flop to an initial state independent of the clock. Shown below is a D flip-flop with clear and preset inputs.

The small circles (inversion symbols) on these inputs indicate that a logic 0 is required to clear or set the flip-flop. This type of input is referred to as active-low because a low voltage of logic 0 will activate the clear or preset function. These inputs override the clock and D inputs. A 0 applied to the clear input will reset the flip-flop to 0 regardless of the values of D and the clock. A 0 applied to the preset input will set the flip-flop to 1 regardless of the values of D and the clock. Under normal operations the clear and preset signals should not both be 0 simultaneously. When both the clear and preset values are logic 1 then the D and clock inputs operate in the normal manner. Shown below is the truth table or the next state table for the D flip-flop with clear and preset inputs.

Shown below is the timing diagram for the D flip-flop with clear and preset inputs.

In synchronous digital systems, the flip-flops are usually driven by a common clock so that all state changes occur at the same time in response to the clock edge. Sometimes situations are encountered where some flip-flips need to hold existing data even thought the data input to the flip-flop may be changing. One way to do this is to gate the clock, shown below on the left. This method has two potential problems. First, gate delays may cause the clock to arrive at some flip-flops at different times than at other flip-flops, resulting in loss of synchronization. Second, if the enable input changes at the wrong time, the flip-flop may trigger due to the change in the enable input instead of the change in the clock, again resulting in a loss of synchronization. A second way to do this is to add a clock enable input to the flip-flop, shown below in the middle. When the enable input is 0, the clock input is disabled and no state change can occur. When the enable input is 1, the flip-flop acts like a normal D flip-flop. This flip-flop can be easily implemented using a MUX, shown below on the right. Because there is no gate in the clock line, this cannot cause a synchronization problem.

Shown below are alternative ways to represent the truth tables or next state tables for the flip-flops discussed in class: Next state table for the D flip-flop:
D 0 1

Q+ = D
Q+ 0 1

## Next state table for the S-R flip-flop:

S 0 0 1 1 R 0 1 0 1

Q+ = S + RQ
Q+ Q 0 1 X

(SR = 0)

## Next state table for the J-K flip-flop:

J 0 0 1 1 K 0 1 0 1

Q+ = JQ + KQ
Q+ Q 0 1 Q

T 0 1

Q+ = T Q
Q+ Q Q

## Next state table for the D-CE flip-flop:

D 0 0 1 1 CE 0 1 0 1

Q+ = D(CE) + Q(CE)
Q+ Q 0 Q 1