Design of LDO Linear Regulator with Ultra Low-

Output Impedance Buffer

Jungsu Choi, Jungeui Park, Wooju Jeong, Junsang Lee, Seok Lee, Jayang Yoon, Jaehoon Kim, and Joongho Choi

Department of Electrical and Computer Engineering

University of Seoul
Seoul, Korea
jchoi@[Link]

Abstract— This paper presents a low-dropout (LDO) linear due to internal compensation and large quiescent current of the
regulator using ultra-low output resistance buffer for frequency regulator as the load current is increased.
compensation. The proposed buffer achieves ultra low output
impedance with dual shunt feedback loops, which makes it In this paper, a novel buffer with ultra low output
possible to improve load and line regulations as well as the impedance is proposed. The buffer makes it possible to extend
transient response for low voltage applications. A reference the internally-generated pole frequency due to large parasitic
control scheme for programmable output voltage of the LDO is capacitance of the driving pass transistors far beyond the cross
presented. The designed LDO linear regulator works under the over frequency in order to enhance the stability of the feedback
input voltage of 2.5~5.5V and provides up to 300mA load current system.
for an output voltage range of 0.6~3.3V.
II. STRUCTURE OF LDO LINEAR REGULATOR
Keywords-component; LDO, Linear Regulator, Ultra-Low
Output Buffer, Compensation, Programmable Output Voltage The circuit schematic of the conventional LDO linear
regulator with the internal buffer is shown in Fig. 1. The
conventional LDO mainly consists of an error amplifier, buffer,
I. INTRODUCTION pass transistor, and feedback resistors (Rfb1 and Rfb2). The error
As the use of the battery-powered portable devices such as amplifier generates the error signal by comparison between
mobile phones, laptops, and various handheld devices has been reference voltage and feedback signal from a resistive-divided
rapidly increased, power management should be one of the output voltage.
most important issues for maximizing the battery lifetime and
providing the energy to multiple on-chip blocks. There are
various power management modules such as switch mode DC-
DC converter, charge pump, and linear regulators. Although
power efficiency of the linear regulator can’t be compared to
the switching regulators, it must be the essential power devices
in the areas such as noise-sensitive RF circuits thanks to low
output noise. In addition, low-dropout linear regulator can be
optimal power management solution for applications where
hardware resources and external off-chip components become
the critical issues due to cost-competitiveness.
In LDO linear regulator design, one of the most important
issues should be stability in various operating conditions. Many
frequency compensation schemes are proposed and used in Figure 1. Convertional LDO linear regulator using buffer compensation.
order to keep the stability of the regulator. The most popular
and simple approach is to use the equivalent series resistance There are several performance issues of the LDO linear
(ESR) of the output capacitor to form the left half plane (LHP) regulator in terms of line and load regulations, power-supply
zero frequency. This method suffers from poor transient rejection ratio (PSRR), load current and dropout voltage. In
responses due to inaccuracy of the value of ESR for different order to increase the loop gain for high regulation and PSRR
operating conditions [1, 2]. There is another scheme that performance, large voltage gain of the error amplifier should be
generates an internal LHP zero, but it is hard to be applicable needed, which can be obtained by using large output resistance
for low supply voltage applications [3]. Pole-splitting by of the amplifier. In order to drive large load current and
nested-miller capacitor can be also used for enhancing stability achieve low-dropout performance, the pass transistor should
of the circuit [4-6]. However this scheme demands large area have large W/L ratio. In this case, pole generated by the error
amplifier output resistance and parasitic capacitance of pass

This research work was supported by “System IC 2010” project of Korea

Ministry of Knowledge Economy and CAD tools are supported by KAIST
IDEC.

978-1-4244-5035-0/09/$26.00 ©2009 IEEE -420- ISOCC 2009

transistor might cause system instability and correspondingly III. PROPOSED BUFFER W/ LOW IMPEDANCE
large value of output capacitor with proper ESR are required, Circuit schematic of the proposed buffer is presented in Fig.
which deteriorates the bandwidth of the regulator. 3. The input PMOS transistor M1 can drive the output pass
The buffer prevents the circuit from operating in such an transistor because it can be more efficient at the light load than
unstable condition by using its low input capacitance and NMOS transistor does. There are dual shunt feedback loops in
output resistance characteristic. A dominant pole p0 composed this buffer. One loop is composed of M1 and M2. The other
of output load capacitor CL and equivalent output resistance loop is composed of M1-M3-M4. The dual shunt-feedback
Rout that can be obtained as [ro,mp || (Rfb1+Rfb2) || Rload], where network increase the feedback gain so that the output resistance
ro,mp is the output resistance of the error amplifier. The second of the buffer can be made much lower than the conventional
pole p1 is generated from output resistance of the error one with single feedback. The output resistance of the proposed
amplifier ro,ea and capacitance that mainly results from the buffer ro,Buf is shown as,
input capacitance Ci,buf of the buffer. The third pole p2 is
1
generated from buffer output resistance ro,Buf and parasitic ro , Buf ≈ (4)
capacitance CP of the large size pass transistor. These three g m1g m 2 ro1 + g m1g m 3g m 4 ro1ro 3
poles can be obtained as,
where gm and ro are transconductance parameter and output
1 GGGG GGGGG GGGGGGG(1)G resistance of each transistor, respectively. The second term of
p0 =
2π ⋅ R out ⋅ C L the denominator can significantly reduce the output impedance
1 of the buffer by the order of magnitude. The improved output
p1 = G G GGGGGGG(2PG
resistance of the buffer can also reduce the bias current of main
2π ⋅ [Link] ⋅ Ci ,buf
buffer transistor M1.
GGGGGGGG G GGGGGGG p = 1 G G GGGGGGG(3)G
2
2π ⋅ [Link] ⋅ C P In addition, the proposed buffer can be preferred for the
low supply voltage operations. Figure 4 shows the simulation
In (1), Rout depends upon the value of load current ILoad and results which compare the output resistance ro,Buf of three
the location of the dominant pole p0 varies with load current buffer structures previously mentioned with respect to buffer
(Rout ĝ 1/Iload). Frequency compensation is usually performed input voltage. Low and high input voltage implies the low
at maximum load case where the regulator might have worst supply voltage operations and heavy load conditions,
frequency response [7]. As shown in (2) and (3), Ci,buf and ro,buf respectively. The results show that proposed buffer gives much
should be very small and the corresponding pole frequencies, lower ro,Buf over all input range owing to the second shunt
p1 and p2 can be high enough so that sufficient phase margin feedback loop operation. This implies that the LDO using the
can be achieved for stable operations. proposed buffer can drive heavy load stably at low voltage
application.
A source follower or super source follower can be used to
implement the buffer. The conventional source follower is
shown in Fig. 2(a). The output resistance of the buffer ro,Buf is
inversely proportional to the transconductance of the transistor
M1. To lower the vale of output resistance, the bias current IB1
or W/L ratio of M1 should be increased. Increased parasitic
capacitance Ci,buf results in poor frequency response and large
power dissipation can’t be avoided. The super source follower
shown in Fig. 2(b) can be incorporated to reduce the output
resistance of the buffer with shunt feedback of the transistor M3
[6]. In the low-supply voltage applications, the low input
voltage might make the input transistor M2 operate in the linear
region, which increases the output resistance. This feature
implies that the regulator is hard to achieve stability when the Figure 3. Circuit schematic of the proposed buffer.
LDO drives large load current at low supply voltage.
Output Resistance (dB)

(a) (b)
Figure 2. Source follower circuits. Figure 4. Output resistance comparison of the 3-buffers
(a) Conventional source follower (b) Super source follower

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 Figure 5. Schematic of the LDO using proposed buffer

regulator are shown in Fig. 6. Simulations are performed at no

IV. DESIGN OF THE PROPOSED LDO REGULATOR load current condition and full load condition of 300mA. At no
The schematic of the entire LDO linear regulator using the load condition the loop DC gain is 78.2dB and the phase
proposed buffer is presented in Fig. 5. Output voltage can be margin is 51º. At full load condition, the DC gain is 68.2dB
programmable using 5-bit digitally controlled reference and the phase margin is 89º.
generator which controls the reference voltage of the regulator.
The error amplifier consists of the PMOS differential amplifier Full Load
and folded output stage of M1~M10, in order to improve the No Load

noise performance and suitable quiescent operating conditions,

respectively. The proposed buffer consisting of MB1~MB11 is
incorporated. Diode-connected NMOS transistor MB10 is used
to generate fixed gate bias voltage of the CG amplifier in the
Full Load
second feedback of the buffer under various input voltage
changes. Additional CB is used as a bypass capacitor which No Load

prevents the feedback path amplifying a high frequency

component. The output pass transistor MP the size of which is
100,000um/0.5um is used. Large external feedback resistors Rf-
Frequency (Hz)
b1 and Rfb2 are used for minimizing the quiescent current of the
regulator. Figure 6. Loop gain analysis of the LDO
Using the proposed buffer, a non-dominant pole due to Programmable output of the LDO linear regulator should be
large gate capacitance of the pass transistor can be sufficiently preferred for the embedded power management integrated
higher than unit-gain frequency of the regulation loop. Thus the systems since various supply voltages are needed for further
loop gain characteristic of the LDO regulator can be reduced to dynamic control schemes. The digital control used in this
two-pole system, where non-dominant pole is generated at the regulator is shown in Fig. 7. It consists of voltage-to-current
output node of error amp and dominant pole is located at the converting circuit, resistor divider, and switch array with 5-to-
output node of the regulator. These two poles are separated 32 decoder.
using current buffer compensation scheme that is achieved by
compensation capacitor CC and common-stage current buffer
M8. This scheme reduces the value of the output load capacitor
for stability. Additional circuit or resistor is not needed to
compensate right-half-plane zero due to feed-forward path of
conventional Miller compensation [6, 8].
The loop gain characteristics of the linear regulator are
greatly changed according to the load current because the trans-
conductance parameter and output resistance of a pass are
varied. Stability analysis of various load conditions is needed
to guarantee stable operations in overall load current. The
simulated loop gain characteristics of the designed LDO Figure 7. Block diagram of the digital controlled reference generator.

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 V. IMPLEMENTATION RESULTS TABLE I. PERFORMANCE SUMMARY

The LDO linear regulator is implemented in a 0.18-um Process 0.18um CMOS

double-poly five-metal CMOS process. Input voltage range is
Input Voltage 2.5~5.5V
2.5~5.5V so that the regulator can be used for the lithium-ion
battery applications. Load current can be 0~300mA in order to Output Voltage 0.6~3.3V
satisfy various PMIC load current requirements. The digitally-
Dropout Voltage 120mV
programmable 32-output voltage ranges from 0.6V to 3.3V is
achieved and provides the accurate desired output voltage in Min. Load Capacitor 1uF
spite of changing operating environments. The quiescent
IMax 300mA
current of the linear regulator core is 130uA over all load
currents. PSRR > 45dB

Load and line regulation transient responses of the Quiescent Current 130uA
proposed LDO regulator are shown in Fig. 8 (a) and (b), Load Regulation 1.8mV ( 6uV/mA )
respectively. The output of the regulator is set to be 2.0V and
full load and line variations are applied. By incorporating the Line Regulation 5.1mV ( 1.7mV/V )
proposed buffer, the LDO linear regulator operates with fast
transient response without any instability. A output capacitor of
1uF with 30m¡ ESR is used for simulation. Table 1 shows the VI. CONCLUSION
summary of the designed LDO linear regulator performance. In this paper, a novel ultra-low output resistance buffer is
proposed for LDO application. The buffer significantly reduces
the output resistance that can be helpful for stable frequency
responses by increasing the non-dominant pole frequency. The
proposed buffer can make the LDO linear regulator drive large
load current, especially for low supply voltage applications. A
5-bit digital controlled reference generator for external MCU
interface is introduced. The circuit is designed and fabricated in
a 0.18-um CMOS technology.

ACKNOWLEDGMENT
This research work was supported by “System IC 2010”
project of Korea Ministry of Knowledge Economy and CAD
tools are supported by KAIST IDEC.
(a)

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Vout (V)

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Figure 8. Transient responses of the regulator.
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