IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO.

10, OCTOBER 2010 757

A Fast-Transient Low-Dropout Regulator With

Load-Tracking Impedance Adjustment and
Loop-Gain Boosting Technique
Pui Ying Or and Ka Nang Leung, Senior Member, IEEE

Abstract—A low-voltage fast-transient low dropout (LDO)

regulator compensated by an off-chip, low-equivalent-series-
resistance (ESR), nanorange output capacitor is reported in this
brief. The proposed load-tracking impedance adjustment and the
loop-gain boosting technique make the proposed LDO regulator
have fast response and small voltage spikes. The circuit is imple-
mented by a commercial 0.35-μm CMOS technology. The chip
area is 0.032 mm2 . The supply voltage ranges from 1.5 to 3 V.
The regulated voltage is 1.2 V to provide 0–100 mA. The quiescent
current in the no-load condition is 26 μA. A 100-nF low-ESR
capacitor is sufficient to stabilize the proposed LDO regulator. The
measured voltage spike is 44.9 mV only, and the response time is
less than 0.2 μs.
Index Terms—Low-dropout (LDO) regulator, low-equivalent-
series-resistance (ESR) capacitor.
Fig. 1. Typical load transient responses of the LDO regulator (for a fixed
COUT ) with (a) a faster response and a lower-ESR capacitor, (b) a slower
I. I NTRODUCTION response and a lower-ESR capacitor, and (c) a slower response and a larger-
ESR capacitor.

R ECENTLY, emerging low-voltage IC systems have been

driven heavily by rapid development of the semiconduc-
tor technology. However, power consumption of modern IC
systems is not necessarily low under a low supply voltage,
since high chip density provides opportunities to include more
and faster functionalities into a chip. Hence, the power con-
sumption, in contrast, is kept increasing. The growing trend of
high power consumption of the modern IC systems working
under a low supply voltage implies that the current consumption
is going to be large. When a low-dropout (LDO) regulator
provides a regulated supply voltage to the low-voltage IC
system, the high supply-current requirement makes the LDO
design become extremely challenging since it is not easy to
suppress the output voltage spikes ΔVOUT of the LDO regula-
tor under rapid and large load transient changes ΔIOUT during
the switching between different operational modes of the IC
system. The general practice is to make use of a large off-chip
capacitor at the LDO output, i.e., COUT , with low equivalent
series resistance (ESR), i.e., RESR , since an LDO regulator
has a nonzero response time Tr , which closely relates to the
unity-gain frequency (UGF) of the LDO loop-gain response. A
Manuscript received March 22, 2010; revised May 25, 2010; accepted
June 15, 2010. Date of publication August 30, 2010; date of current version
October 15, 2010. This work was supported by a grant from the Research Grants
Council of Hong Kong SAR Government under Project CUHK414408. This
paper was recommended by Associate Editor P. Mohseni.
The authors are with the Department of Electronic Engineering, The Chinese
University of Hong Kong, Shatin, Hong Kong (e-mail: pyor@ee.cuhk.edu.hk;
knleung@ee.cuhk.edu.hk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2010.2058590
larger COUT is helpful to supply transient current to the load
circuit when the LDO regulator cannot respond to rapid load
changes. Moreover, a smaller RESR can significantly reduce
transient voltage spikes. In fact, the magnitude of the output
voltage spike is approximately given by
ΔVOUT ≈ (ΔIOUT /COUT ) · Tr + ΔIOUT RESR . (1)
Fig. 1 shows the typical load transient response of an LDO
regulator with a fixed COUT . The smallest voltage spikes
among the three cases can be achieved by a faster LDO response
and a smaller RESR . Moreover, a generic LDO regulator shown
in Fig. 2(a) uses dominant-pole compensation with single pole-
zero cancellation, as shown in Fig. 2(b). The zero zESR is
generated by the ESR of COUT to cancel the nondominant
pole p2 [1]. The dominant pole p1A is inversely proportional
to COUT [1]. When a larger COUT is used, the UGF is reduced,
and thus, the response time is degraded, since the dominant pole
is shifted to a lower frequency (i.e., p1B ). As a result, including
the concern of the cost and the physical size of the off-chip
capacitor, COUT is suggested to be small to improve the re-
sponse time, but it should be large enough to be able to achieve
the stable closed-loop LDO operation simultaneously. In fact,
when COUT is reduced, RESR has to be increased to generate
the ESR zero at the same frequency to achieve an effective pole-
zero cancellation (i.e., zESR = 1/(COUT RESR )) [1]. It causes
larger transient voltage spikes. Thus, there is a contradiction
between the stability and the transient-response improvement.
With regard to the above concerns, in this brief, a 100-mA
LDO regulator compensated by an off-chip, low-ESR,

1549-7747/$26.00 © 2010 IEEE

758 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010
Fig. 2. (a) Generic LDO regulator. (b) Typical loop-gain responses with
different output capacitances (the used ESR values in both cases are different
to maintain the same zESR position).
nanorange output capacitor will be presented in Section II. The
goal of the design is to achieve a fast transient response with
small voltage spikes. Section III will report the measurement
results. Finally, a comparison with some recently reported LDO
designs using a low-ESR capacitor will be given in Section IV.
II. P ROPOSED LDO S TRUCTURE
The proposed LDO regulator is shown in Fig. 3(a). It is
formed by an LDO structure shown in Fig. 3(b), which has
been analyzed in [5] in detail. In Fig. 3(a), MPT is the power
transistor, whereas MC1 is the common-gate error amplifier
with a folded structure formed by M01 , M02 , and M04 to have
the output at node Y. This structure includes a load-tracking
impedance adjustment circuit formed by the diode-connected
M07 to change the impedance at node Z for the use of low-
ESR low-capacitance capacitor and a loop-gain boosting circuit
formed by M05 and M06 . Details of the proposed techniques
will be analyzed later in this section. Similar to the design
reported in [5], a control-voltage generator (i.e., to generate VX
to define the gate voltage of MC1 ) is formed by MA1 −MA7
and MC2 . The simple setup composed of the reference voltage
VREF , RB , and a diode-connected MB1 provides the bias
current to the whole circuit. It is noted that CB is a filtering
capacitor to keep the bias current away from the effects of
coupling signals and noise.
Based on the analysis reported in [5], there are totally three
left-half-plane (LHP) poles and one LHP zero (the ESR zero).
When referring to the ultimate goal to use a low-ESR capacitor
for improving the transient response, one of the nondominant
poles and the ESR zero are located after the UGF due to the
low ESR value, and thus, they can be neglected in the analysis.
Finally, the dominant pole of the proposed LDO regulator is
given by [5]
  −1
−1
p1 = COUT roPT //gmC1 (2)
where roPT is the drain resistance of MPT , and gmC1 is the
transconductance of MC1 . There is only one nondominant pole
left in the proposed design. It is given by [5]
   −1

p2 = CgsPT + CgdPT 1 + gmPT roPT //gmC1
 −1
−1
× ro5 //ro6 //gm7 (3)
where CgsPT and CgdPT are the gate-to-source and gate-to-
drain parasitic capacitances of MPT , respectively. Since MPT
is not small, both CgsPT and CgdPT cannot be neglected in the
analysis. From (3), it is found that p2 relates to the transconduc-
tance of M07 (i.e., gm7 ). When referring the connection of M07
in Fig. 3, it detects the source-to-gate voltage of MPT directly.
As a result, the drain current of M07 is proportional to IOUT ,
and this makes p2 locate at a higher frequency when IOUT
increases.
Fig. 4(a) shows the conceptual diagram of the loop-gain
response without M07 . When IOUT increases, the output resis-
tance of the LDO regulator decreases, and thus, the loop gain
is reduced for higher IOUT . Moreover, according to (2), p1 is
shifted to a higher frequency, whereas p2 remains unchanged if
M07 is not included in the design. As a result, both p1 and p2
are located before the loop-gain UGF, and the LDO regulator is
not absolutely stable within the full range of IOUT .
When M07 is included, p2 is dependent of gm7 , as shown
in (3). A higher IOUT will push p2 to a higher frequency and
beyond the loop-gain UGF after careful design of the size ratio
between MPT and M07 with a reasonable low current consumed
by M07 . It will be proved experimentally in Section III that this
additional current is not large. However, as shown in Fig. 4(b),
the overall loop gain is dramatically reduced due to the im-
pedance reduction by the diode-connected M07 . Thus, M05 and
M06 are added to compensate the loop-gain loss. The loop gain
−1 −1
is −gmp (roPT //gmC1 )gmC1 (ro2 //ro4 )gm6 (ro5 //ro6 //gm7 ),
and thus, the UGF is given by
  −1

UGF = gmp gmC1 gm6 (ro2 //ro4 ) ro5 //ro6 //gm7 /COUT .
(4)
As shown in Fig. 4(c), both the loop gain and the UGF
are improved. The condition to select the value of COUT is
to ensure p2 always locating after the UGF in the maximum
IOUT condition. The design of the gate size of M06 is important
so that the parasitic effect at node Y will not generate a pole
locating before the loop-gain UGF. From a circuit simulation,
it is found that ro2 = 2.19 MΩ, ro4 = 1.86 MΩ, and Cg6 =
38.84 fF. The pole at Y is located at 4.07 MHz, which is
higher than the UGF of about 1 MHz. This result shows that the
pole created at node Y does not affect the phase margin of the
loop gain.
Moreover, the large-signal response of the proposed LDO
regulator is not a limiting factor to the response speed in this
design, since the slew rate at node Z (due to the large gate
capacitance of MPT ) is not limited in this structure. When
VOUT is deviated from the preset value, the gate voltage of
MPT will be adjusted by the feedback. M05 and M06 are
responsible to drive the gate capacitance of MPT to achieve the
OR AND LEUNG: LDO WITH LOAD-TRACKING IMPEDANCE ADJUSTMENT AND LOOP-GAIN BOOSTING TECHNIQUE 759

Fig. 3. (a) Proposed LDO structure. (b) LDO circuit reported in [5].

Fig. 4. Conceptual diagrams of the loop-gain responses. (a) Without M07 . (b) With M07 and without M05 and M06 . (c) With M05 , M06 , and M07
(not in scale).

Fig. 5. Chip micrograph of the proposed LDO regulator.

adjustment. Since the pole created at node Y should be at a high

frequency to ensure the closed-loop stability, the size of M06 is
not large. However, the dynamic discharging current by M06 is
not small, as it is now mainly determined by its gate-to-source
voltage, which has a dynamic range between VIN − VSD04(sat)
and VDS02(sat) . Thus, the discharging of node Z is not a problem
toward the response time of the proposed LDO regulator. On the
charging side, the extra current from M07 does help the transient
response at node Z. Due to the above considerations, the design
of the steady-state bias current for M05 and M06 does not need
to be high.
III. E XPERIMENTAL R ESULTS
The proposed LDO regulator is implemented in austriami-
crosystems (AMS) 0.35-μm 2-poly 4-metal CMOS technology.
The micrograph is shown in Fig. 5, and the chip area is
250 μm × 128 μm (0.032 mm2 ), excluding the test pads.
Fig. 6. Relationship between IQ and IOUT .
The threshold voltages of the NMOSFET and PMOSFET in
the used technology are about 0.5 and −0.65 V, respectively.
The LDO regulates the output voltage at 1.2 V from a supply
ranging from 1.5 to 3 V, whereas the load current is from 0 to
100 mA. The loop gain is about 40 dB. As will be proven by
the measured load transient responses shown in Figs. 7–12, the
proposed LDO regulator is stable when COUT = 100 nF, and
it is also stable in a wide range of COUT ranging from 100 nF
to 10 μF. The ESR values of the used capacitors are on the
order of several or tens of milliohms. It shows that the stability
of the proposed LDO regulator does not need the help from the
ESR zero.
Fig. 6 presents the quiescent current IQ against the out-
put current. In the no-load condition, the LDO regulator
consumes 26 μA only. At the maximum output current
760 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010

Fig. 7. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 0−100 mA, COUT = 100 nF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.

Fig. 8. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 0−100 mA, COUT = 200 nF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.

Fig. 9. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 0−100 mA, COUT = 4.7 μF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.

Fig. 10. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 1−100 mA, COUT = 100 nF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.

Fig. 11. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 1−100 mA, COUT = 200 nF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.
OR AND LEUNG: LDO WITH LOAD-TRACKING IMPEDANCE ADJUSTMENT AND LOOP-GAIN BOOSTING TECHNIQUE 761

Fig. 12. Measured load transient response for VIN = 1.5 V, VOUT = 1.2 V, IOUT = 1−100 mA, COUT = 4.7 μF, and added RESR = 0. (a) Full view.
(b) Zoom-in view of the undershoot. (c) Zoom-in view of the overshoot.

(i.e., IOUT = 100 mA), although a higher bias current is used TABLE I
C OMPARISON OF S OME S ELECTED LDO D ESIGNS
for impedance reduction by M07 , IQ remains below 70 μA. U SING A L OW-ESR C APACITOR
Some measured load transient responses of the proposed
LDO regulator are shown in Figs. 7–12.
Both cases of IOUT = 0−100 mA and IOUT = 1−100 mA
are included, since the load regulation cannot be accurately
observed in the cases of IOUT = 0−100 mA. The reason is that
the overshoot of VOUT causes COUT to be overcharged, but
COUT cannot be discharged by the LDO regulator internally
due to the low bias current. Thus, the cases of 1–100 mA
are included for the sake of observing the load regulation.
Moreover, in all measurements, IOUT is switched between 0
(or 1 mA) and 100 mA within 100 ns.
In Fig. 10, when the LDO regulator is connected with a
100-nF output capacitor, it shows stable operation with a re-
sponse time faster than 0.2 μs. The undershoot and overshoot of
VOUT are 30.3 and 44.9 mV, respectively. The load regulation
is 8 mV/99 mV. The fast response time of 0.2 μs implies that
[2]–[5], the minimum value of the off-chip capacitor is 1 μF,
the loop-gain UGF is high, but it is the boundary condition
but the proposed LDO regulator can be stabilized by a
of stability (since slight ringing is observed) when using a
100-nF capacitor. The quiescent current and the voltage spikes
100-nF capacitor. When a 200-nF capacitor is used (Fig. 11),
of the proposed design are not large when compared with
the response time is slightly more than 0.2 μs, but it shows
others. Finally, the proposed LDO regulator has the fastest
better stability (no ringing). The voltage spikes are similar
response time of 0.2 μs.
to the case using a 100-nF capacitor. This proves the design
consideration for COUT stated in Section II.
Figs. 9 and 12 are the transient responses when using a V. C ONCLUSION
4.7-μF capacitor. The voltage spikes are reduced to about
20 mV, as the larger capacitor provides more transient current A low-voltage fast-response small-voltage-spike LDO regu-
to the load. However, a larger capacitor degrades the response lator with load-tracking impedance adjustment and loop-gain
time, since the loop-gain UGF is significantly reduced. Thus, boosting technique has been presented. It has been proven
the proposed design makes a 100-nF capacitor sufficient to that it can be stabilized by an off-chip, low-ESR, nanorange
achieve fast response and small voltage spikes simultaneously. capacitor. The design is suitable for low-voltage high-current
Finally, the stability of the proposed LDO regulator is tested applications.
with an added ESR ranging from 0.1 to 0.5 Ω. It is verified that
the LDO regulator is perfectly stable in all cases. There are R EFERENCES
two remarks for this measurement. When COUT is small (i.e., [1] J. Falin, “ESR, stability and the LDO regulator,” Texas Instruments, Dallas,
100 nF, 200 nF, etc.), the ESR zero locates after the loop-gain TX, Texas Instruments Application Report SLVA115, May 2002.
[2] W.-J. Hung, S.-H. Lu, and S.-I. Liu, “CMOS low dropout linear regulator
UGF. However, it still has a slight effect to cancel p2 , and thus, with single Miller capacitor,” Electron. Lett., vol. 42, no. 4, pp. 216–217,
for the case of using a 100-nF capacitor, the slight ringing Feb. 2006.
vanishes when the added ESR ranges from 0.1 to 0.5 Ω. [3] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient enhanced low-quiescent
Moreover, when COUT is on the order of μF, the UGF is current low-dropout regulator with buffer impedance attenuation,” IEEE J.
Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742, Aug. 2007.
reduced so that the ESR zero does not affect stability since it is [4] H.-C. Lin, H.-H. Wu, and T.-Y. Chang, “An active frequency compen-
located far beyond the UGF. sation scheme for CMOS low-dropout regulators with transient-response
improvement,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 9,
pp. 853–857, Sep. 2008.
IV. C OMPARISON [5] T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok, and M. Chan,
“Development of single-transistor-control LDO based on flipped voltage
Some reported LDO designs utilizing a low-ESR capac- follower for SoC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 5,
itor is summarized in Table I. For the designs reported in pp. 1392–1401, Jun. 2008.