Fast transient capacitor-less LDO regulator The response of an LDO to a load current change is characterised in two

using low-power output voltage detector
Y.-I. Kim and S.-S. Lee
An output-capacitor-less low-dropout regulator (LDO) with a low-
power output voltage detector (OVD) is proposed. The OVD is based
on an R/C highpass filter which is able to detect the fast-changing
voltage at the LDO output and activate an additional path to control
the power transistor. The OVD consumes only additional quiescent
current to monitor the variation in output voltage in the steady state.
In the simulated load-transient response, a maximum undershoot of
1.2 V and a settling time (Dt2) of 67 ns are observed with the proposed
OVD for a load current variation from 1 to 50 mA at a rise time of 1 ns.
These results are 0.2 V and 473 ns better than the results obtained
without the proposed OVD.
Introduction: Currently, low-dropout (LDO) regulators are widely used
in battery-powered mobile systems, which require small size and a clean
supply voltage. To prolong battery life and to improve power efficiency,
reductions in the quiescent current and the dropout voltage are necess-
ary. However, a low quiescent current unavoidably slows the transient
responses of an LDO regulator. Minimising the quiescent current and
dropout voltage to increase power efficiency while maintaining good
regulation and a fast response time is the main issue of LDO regulator
design [1]. For portable applications, external components such as
output capacitors should be minimised to reduce the printed circuit
board (PCB) layout space and to speed up the manufacturing process,
so an output capacitor-less LDO regulator is preferred. However,
because of the limited on-chip size, the internal on-chip output capacitor
is smaller and the ESR is increased. This will lead to severe output
voltage changes during a fast-load current transient [1]. Recently,
many researchers have proposed various strategies for improving the
power efficiency and the transient response performance of the output
capacitor-less LDO regulators. Using the capacitor coupling effect for
the transient response performance [1 – 3] and modifying the driver of
the power transistor to improve the slew rate have been proposed [4].
However, these methods need additional circuitry and current, which
causes considerable degradation of the power efficiency.
sections: the initial step responses of Dt1 and Dt3 and the settling times
of Dt2 and Dt4. The step response represented by Dt1 in Fig. 1 is a
function of the ERR AMP bandwidth (BW) and ISR , and Dt1 is given by
1 DV
Dt1 ≃ + Cp (1)
BW Isr
where BW is the closed-loop bandwidth of the LDO negative feedback,
DV is the voltage variation at the gate of the PWR TR, and ISR is the
current for driving the Cp of the PWR TR. To minimise Dt1 and Dt3 ,
the LDO requires a wide closed-loop BW and a higher SR. Also, by
using a small output capacitor and a higher SR for driving the Cp, the
settling times of Dt2 and Dt4 can be minimised [6].
Proposed scheme description: As shown in Fig. 1, the LDO undergoes
a small-signal response when the output current of the LDO increases
(or decreases) rapidly over the BW of the LDO. The LDO cannot instan-
taneously respond to the charge needed to decrease (or increase) the
PWR TR gate voltage owing to the limited BW. The LDO produces a
large signal response when there is a large change in the load current.
The decrease (or increase) of the gate voltage of the PWR TR is
constrained by the limited SR of the driver for the PWR TR.
Immediately, a rapid and large change in load current causes a serious
problem in the initial peak voltage drop and the settling time. The
proposed LDO in this Letter is formed by an OVD which has a
higher frequency range than the main loop bandwidth, as shown in
Fig. 2. The OVD is based on an R/C highpass filter (HPF), which is
implemented by a simple RC structure [7]. The sensing parts of the
OVD always activate to monitor the variation in output voltage, but
the other MP_UP, MN_DN , MP_ONOFF, and MN_ONOFF transistors are
deactivated in steady state operation. When a rapid and large change
in load current is detected, an additional path that has a wide BW and
low gain is activated to control the PWR TR. The full circuit with the
OVD is shown in Fig. 3.
VIN
ERR_AMP
Vref
buffer
+

Pwr. Tr.
To solve these problems, the output voltage detector (OVD) is based
on a highpass filter (HPF) that is able to detect the initial peak output – OVD
C
voltage. The sensed signal activates an additional path to control the output voltage
Vout
detector
power transistor to improve the load-transient response. For low-power

ESR
operation, the OVD block consumes only additional quiescent current R1
to monitor the variation in the output voltage in steady state.
Cout

R2 GND
Vout t3

Iout t4 GND

Iout

Vout LDO main loop bandwidth

overlapping

frequency

t2
output voltage detector

t1

time, s Fig. 2 Frequency range of OVD and block diagram

Fig. 1 Transient response of step load current VIN

< OTA > < buffer > < output voltage detector >
5uA 10uA 5uA 10uA 15uA ON/OFF 5uA ON/OFF 1.5uA 1.5uA ON/OFF 1.5uA 1.5uA Iq_tot=46uA
MP_ON/OFF

Vb1
MP_UP

VB1 Vb3

LDO description: Fig. 2 displays a three-stage LDO regulator structure VA

MNA
P.W.R Tr.

consisting of an error amplifier (ERR-AMP), buffer (BUF), a power Vref VFB

Vout CA
1
+
rop Vout
CB

transistor (PWR TR), and feedback resistors. The ERR-AMP generates gmn gmnron
MN_ON/OFF

ESR
MNB

R1
VFB
the error signal based on a comparison between the reference voltage Cout VB
MN_DN

and the feedback signal from a resistive-divided output voltage. In the
output-capacitor-less LDO structure, the dominant pole is located in
the PWR TR gate node, not in the output node. Therefore, using a
buffer with low input capacitance and a high output resistance character-
istic guarantee the stability of the circuit operation [5]. To supply a large
output current, the PWR TR has to be large compared to the other tran-
sistors. Therefore, the parasitic capacitor (Cp) at the gate of the PWR TR
is very large, in the range of tens to hundreds of picofarads. A large Cp
limits the slew rate performance. Fig. 1 shows the details of a typical
LDO response to a load current step. The transient response time of
an LDO to a load current step is a critical specification in applications.
Vb2 Vb4
R2
GND
Fig. 3 Full circuit with OVD
(i) Undershoot: When the load current increases suddenly, the output
voltage undershoot increases dramatically. This signal will couple
through CA and amplify through MN_A and MP_ONOFF transistor acti-
vation. The additional drain current of MN_DN will then flow from the
Cp of the PWR TR gate to supply additional output current. As a
result, the output of the undershoot can be recovered more quickly.

ELECTRONICS LETTERS 2nd February 2012 Vol. 48 No. 3

 (ii) Overshoot: When the load current decreases suddenly, the output Conclusion: Presented is a method to improve the load-transient
voltage overshoot increases dramatically. This signal will couple response of the output-capacitor-less LDO using a low-power OVD.
through CB and will amplify through MP_B and MN_ONOFF transistor The proposed OVD consists of two R/C HPFs which are able to
activation. The additional drain current of MP_UP will then flow to the detect the fast-changing peak drop voltage at the LDO output and acti-
PWR TR gate to reduce the output current. As a result, the output of vate an additional path to control the power transistor to improve
the overshoot can be recovered more quickly. responses. The proposed OVD consumes only additional quiescent
Since all of the nodes in this signal path are connected to a small current to monitor the variation in the output voltage in the steady
parasitic capacitance and consist of a low impedance node, this signal state. This scheme solves the problems of limited BW and SR in the
propagation time is expected to be fast. Therefore, the proposed LDO conventional LDO by applying a simple and effective modification to
will have good performance in terms of undershoot/overshoot. the LDO circuit.
In the steady state, the VA voltage level is set between VDD 2 |VTHP|
to VDD 2 VOD and the VB voltage level between VOD to VTHN by the Acknowledgments: This work was supported by ‘BK21’, ‘IDEC’ and
current mirror configuration, so the MP_UP, MN_DN , MP_ONOFF, and ‘HYNIX’.
MN_ONOFF transistors are deactivated for low-power operation. The
common mode feedback circuit (CMFB) could be used for more # The Institution of Engineering and Technology 2012
robust VA and VB voltage levels. The CMFB signal loops are from 8 December 2011
VA to Vb2 and from VB to Vb3 , respectively. doi: 10.1049/el.2011.3671
One or more of the Figures in this Letter are available in colour online.
Simulation results: This LDO is implemented in a 110 nm CMOS tech-
nology provided by Dongbuhiteck. The internal output capacitor is 5 nF Y.-I. Kim and S.-S. Lee (Department of Nanoscale Semiconductor
and the ESR is 1 V. The LDO output voltage ranges from 1.6 to 3.6 V Engineering, Hanyang University, 222 Wangshimniro, Seongdong-gu,
with a minimum dropout voltage of 200 mV and a maximum output Seoul 133-791, Republic of Korea)
current of 200 mA. The LDO operates with a supply voltage ranging E-mail: ssnlee@hanyang.ac.kr
from 1.8 to 3.8 V, and its quiescent current is 46 mA for a 3.3 V
supply voltage, not including the bandgap circuitry, as calculated in References
Fig. 3. Of particular importance is the fact that the proposed OVD 1 Ho, E.N.Y., and Mok, P.K.T.: ‘A capacitor-less CMOS active feedback
block consumes only 6 mA in the steady state. The LDO stability and low-dropout regulator with slew-rate enhancement for portable on-chip
its specifications are ensured for all of the process corners and over a application’, IEEE Trans. Circuits Syst. II, 2010, 2, pp. 80– 84
temperature range from 220 to 1008C. In the simulated load-transient 2 Or, P.Y., and Leung, K.N.: ‘An output-capacitorless low-dropout
response, a maximum undershoot of 1.2 V and a settling time (Dt2) of regulator with direct voltage-spike detection’, IEEE J. Solid-State
67 ns are observed with the proposed OVD for a load current variation Circuits, 2010, 45, pp. 458– 466
from 1 m to 50 mA at a rise time of 1 ns. As shown in Fig. 4, these 3 Leung, K., and Ng, Y.S.: ‘A CMOS low-dropout regulator with a
results are 0.2 V and 473 ns better than the results obtained without momentarily current-boosting voltage buffer’, IEEE Trans. Circuits
the proposed OVD. The simulated loop gain is from 88 to 80 dB, the Syst. I, 2010, 57, pp. 2312–2319
4 Man, T.Y., and Mok, P.K.T.: ‘A high slew-rate push– pull output
unit gain frequency is 9 MHz, and the phase margin is from 558 to amplifier for low-quiescent current low-dropout regulators with
908 for a load current variation from 1 to 200 mA. transient-response improvement’, IEEE Trans. Circuits Syst. II, 2007,
9, pp. 755 –759
ldo
V(out)
V(out)
2.4 Vout
9.6u 9.8u 10u
10/19/2011 03:38:38
10.2u
t2 with PVD = 67nsec
10.4u 10.6u 10.8u
waveview 1
t2 without PVD = 540nsec I_load[mA]
5 Al-Shyoukh, M., and Lee, H.: ‘A transient-enhanced low-quiescent
473nsec is reduced by OVD
2.2 current low-dropout regulator with buffer impedance attenuation’,
2
1.8
2.25V
IEEE J. Solid-State Circuits, 2007, 8, pp. 1732–1742
V[V]
1.6
1.4
VA 6 Oh, W., and Bakkaloglu, B.: ‘A CMOS low-dropout regulator with
1.2
(With OVD) 1.05V
VB
current-mode feedback buffer amplifier’, IEEE Trans. Circuits Syst. II,
1 0.2V is reduced by OVD
i(iout) 50m
I_load
0.85V (without OVD)
I_load I [mA]
2007, 10, pp. 922– 926
40m
50mA I_MN_DN
0A 7 Coulot, T., Rouat, E., Fournier, J.-M., Lauga, E., and Hasbani, F.: ‘High
30m I_MP_UP
0A power supply rejection low-dropout regulator for ultra-low-power
20m Vout[V] radiofrequency functions’, Electron. Lett., 2011, 47, (20), pp. 117 –118
10m
1mA
rising time : 1nsec
9.6u 9.8u 10u 10.2u 10.4u 10.6u 10.8u
printed Wed Oct 19 2011 04:04:04:16 by yikim on localhost.localdomain sec (lin) synopsys, Inc. (c) 2000-2009 time [sec]

Fig. 4 Simulation results

ELECTRONICS LETTERS 2nd February 2012 Vol. 48 No. 3