A NOVEL FREQUENCY COMPENSATION TECHNIQUE
FOR LOW-VOLTAGE LOW-DROPOUT REGULATOR
Ka Nang Leung, Philip K.7: Mok and Wing Hung Ki
Department of Electrical and Electronic Engineering
The Hong Kong University of Science and Technology
Clear Water Bay, Hong Kong, China
Te1:(852)2358-8517 Fax:(852)2358-1485 E-mail:eemok@ee.ust.hk
ABSTRACT
A novel frequency compensation technique for low-voltage
low-dropout regulator (LDR) is presented. The proposed tech-
nique, called pole-control frequency compensation (PCFC), pro-
vides faster loop response and does not require a large filtering
capacitor. Both theoretical analysis and simulation show that the
stability of the LDR using PCFC is independent of the load cur-
rent, temperature and equivalent series resistance of the filtering
capacitor. It is well suited for LDRs inside portable equipment
such as cellular phones, pagers and personal digital assistance.
1. INTRODUCTION
Low-dropout regulator (LDR) is widely used in many portable
equipment such as cellular phones, pagers and personal digital as-
sistance. The stability and accuracy of the regulated supply voltage
directly affect the performance of the portable equipment. In order
to have a stable and accurate supply voltage, not only an optimum
voltage reference and advanced circuit techniques are essential but
the frequency compensation technique to ensure the stability of the
LDR under all operation conditions is also important.
As the supply voltage of analog circuits decreases from 3.3V
to 2V or less, the design of LDRs becomes more challenging. Con-
ventionally, in order to obtain an accurate output voltage, the error
amplifier inside a LDR is implemented by a high-gain single-stage
cascode amplifier. However, cascode amplifier cannot be imple-
mented under low supply voltage, and two-stage cascade amplifier
should be used instead. As will be shown in this paper, the con-
ventional frequency compensation scheme cannot effectively sta-
bilize a low-voltage LDR with a two-stage error amplifier, and the
loop response is slow. Therefore, a new frequency compensation
scheme for low-voltage LDRs needs to be developed.
In order to stabilize low-voltage LDRs, a novel approach based
on nested Miller compensation (NMC) [ 11, [2], called pole-control
frequency compensation (PCFC), is proposed in this paper. This
approach is systematic and improves the stability of a low-voltage
LDR under the change of the load current and temperature. More-
over, the stability of the LDR using PCFC is almost independent
of the equivalent series resistance (ESR) of the filtering capacitor.
The organization of this paper is as follows. In section 11, the
problems of the conventional frequency compensation, notated as
CFC, in low-voltage LDRs are discussed. The proposed scheme
PCFC is presented in section 111. Theoretical analysis on the sta-
bility of the low-voltage LDR using PCFC is explained in detail.
In section IV, simulation results to show the superior stability of
PCFC are included. Finally, conclusion of this paper is given.
0-7803-5471-0/99/$10.0001999 IEEE
v-102
2. PROBLEMS OF THE CONVENTIONAL FREQUENCY
COMPENSATIONSCHEME IN LOW-VOLTAGE LDRS
In this section, the drawbacks of CFC in low-voltage LDRs
are discussed. The structure of a LDR with two-stage error ampli-
fier using CFC is shown in Fig. 1. As the pass transistor provides
negative voltage gain, the feedback signal from the resistive feed-
back network Rfl and Rf2 is fed to the positive input of the er-
ror amplifier. A load resistor RL and a filtering capacitor CL with
equivalent series resistance RESRare connected at the output. The
LDR is stabilized with appropriate values of CL and R E S R .
given by pl = CL(RL:RESR)9p2=
while the ESR zero is given by Z E S R =
&
&
+
There are three poles and one zero in the LDR. The poles are
andp3 = p l RI
where C,, and
CPTare the parasitic capacitance at the output of the first stage
and the input capacitance of the power pass transistor, respectively;
R ( l - 2 )are the output resistance of the first and second stage, re-
spectively. To achieve optimum stability, Z E S R should be equal
to p2 for pole-zero cancellation, and p3 should be placed after the
unity-gain frequency of the loop gain response [3], [4].
In CFC, the unity-gain frequency of the loop gain is constrained
by p3, and p3 is generally at low frequency as RI is large. Thus,
the loop response of the LDR is slow.
To obtain an accurate supply voltage, the DC loop gain should
be very large. As shown in Fig. 2, the position of the first pole
is located at a very low frequency (at P I ) . In order to do so, the
value of CL is needed to be huge and a very small ESR to create
an appropriate ESR zero to cancel p2 is required.
Moreover, the change of the load current will change the posi-
tion of p l . As depicted in Fig. 2, pl is shifted to a higher frequency
@;) for a higher load current (i.e. a smaller RL), and the LDR may
be unstable at certain load current level as p3 may place before the
unity-gain frequency. Therefore, LDR using CFC should be com-
pensated at the maximum load current (the worst case).
The matching of pz and Z E S R is very critical in stabilizing a
LDR. Therefore, either too small or too large ESR will cause the
LDR unstable [3], [4]. Temperature changes will also affect the
position of the poles and ESR zero. However, the amount of fre-
quency shifting of the poles and ESR zero are different because the
temperature coefficients of the output resistance of the gain stages
and the ESR are different. There is no guarantee that p2 will be
cancelled by ZESR after the change in temperature. Thus, the LDR
is stable only within a specific range of operation temperature.
From the above analyses, a LDR using CFC is parameter de-
pendent and is very sensitive to external effect. Therefore, CFC is
limited to certain operation conditions and not optimum.
 Unregulated input voltage (Vln)

Regulated output voltage (Vout)

Filtering
capacitor

Loading
RL redstance

I
Feedfornard
transconductancestage
realatanea

Figure 1: Structure of a LDR with two-stage error amplifier com- Figure 3: Structure of the proposed LDR
pensated by CFC
3.1. Loop Gain Transfer Function and Stability Criteria
IT(s)l Load current Increases It is assumed that R f l and R J Zare much larger than RL,.By
+
setting R , = ( g m f z g m 3 ) - l , the loop gain transfer function
T ( s )= 2 of the proposed structure is given by

where TDC = gmlgm2gm3R1R2R~ is the DC loop gain and

Figure 2: Loop reslponse of a LDR using CFC under two different
load current levels
p-3de = ( C ~ I ~ ~ Z ~ ~ ~ Ris ItheRdominated Z R L ) pole.
- ~ It
should be noted that as the gain of the third gain stage (the pass
transistor) may be less than one, (1) is derived based on the as-
sumption that the product of the voltage gain of the second and
third gain stage is greater than one, and it is always true in LDR
design.
The stability of the LDR is achieved at stand-by state (zero
load current). The stability criteria are obtained by considering
that the poles of the loop gain has third-order Butterworth fre-
quency response in unity-feedback configuration [7]. Let gmss

3. PROPOSED FREQUENCY COMPENSATIONSCHEME

e,
be the transconductance of the pass transistor at stand-by state. By
defining m = 9-2 and IC, = the dimension conditions of
the compensation capacitors are given by
FOR LOW-VOLTAGELDRS

c
7n1 =
1
* - 1) (RfiR+f zR J Z) (=)CL
+ k,(m gm3q
(2)
From the previous section, the main problem of CFC is that
the position of the poles are fixed, and only one of the poles can be
cancelled by the ESR zero. In order to solve this problem, PCFC
is presented in this section. This technique can stabilize a LDR
under the change of the load current and temperature. In addition,
PCFC is independent of the ESR. 3.2. Unity-Gain Frequency and Phase Margin of Loop Gain
The structure of the proposed scheme is shown in Fig. 3. Error By using (2) and (3), the unity-gain frequency (UGF) and
amplifier with two gain stages is used to provide sufficient volt- phase margin (PM) [8] of the loop gain response are given by
age gain. The pass transistor is considered as the third gain stage,
and the transconductance of the stages are notated as ~ ~ ( 1 - 3A) .
nested Miller compensation technique with feed-forward transcon-
ductance stage and null resistor is used in this scheme to split the
poles [SI. As the quiescent current is low and a right-half-plane 1 gm3q + S m f z - Smz
zero deteriorates the phase margin [ 6 ] ,the bandwidth of NMC is =a( CL (4)
poor. An extra feed-forward transconductance stage g m f z and null
resistor R , are added to the structure to optimize the stability. P M M 60" +tan-' (5)

V-103
 Vin
I For the LDR using CFC, a 200pF filtering capacitor with ESR
Feed-forward
transcondudance stage
Figure 4:Circuit diagram of the proposed LDR
where Z L H P is the left-half-plane zero stated in (1). Since it is
generally not necessary to have a PM greater than 60",the value of
C,1 can be reduced to obtain a larger value of the UGF. Moreover,
a smaller integrable filtering capacitor can be used.
3.3. High Load Current Effect
The stability of a LDR using PCFC is achieved at stand-by
state. Since the load current may vary during operation, the stabil-
ity of the LDR in higher load current state should be considered.
From the denominator of (l), the second-order function is ap-
proximated to be a first-order function when the load current is
large (i.e. gm3 is large). Moreover, the zero can be neglected when
g m 3 is large. The position of the second pole is given by
As the position of the second pole always locates after the UGF,
the LDR is stable in the high load current state.
3.4. Temperature Effect
Since the position of the poles as well as the UGF are directly
proportional to the transconductance of the gain stages and do not
depend on other parameters with different temperature coefficient,
the amount of frequency shifting of the poles under the change of
temperature are all the same. Therefore, any increase in tempera-
ture only changes the UGF but not the stability of the LDR.
3.5. ESR Effect
If the ESR of the filtering capacitor is non-zero, an ESR zero is
created and the position of the ESR zero is equal to ( C L R E S R ) - ~ , such as cellular phones, pagers and personal digital assistance.
As explained previously, since PCFC does not require a large fil-
tering capacitor, the position of the ESR zero is located at a higher
frequency than the UGF (typically NlMHz), and the ESR zero
does not affect the stability of the LDR.
4. SIMULATION RESULTS
Low-voltage LDRs using CFC and PCFC were simulated us-
ing HSPICE and a commercial BSIM3v2 0.8pm CMOS model
V-104
from AMS'. The circuit diagram of the LDR compensated by
PCFC is shown in Fig. 4. The LDRs are designed to deliver a
maximum load current of 20mA with 2.3V input and 2V output.
The feed-forward transconductance stage is implemented by MF
connected as shown in the figure. For the CFC counterpart, no
feed-forward transconductance stage, null resistor and compensa-
tion capacitor is used but an ESR in series with the filtering capac-
itor is required to ensure the stability of the LDR. The feedback
resistors R f l and Rfz are changed to ensure that the quiescent
current flowing through the pass transistor is the same for the two
topologies. The design parameters of the LDRs are tabulated in
Table I.
of 25mR is required. However, only a lOOpF filtering capacitor is
needed when using PCFC, and it can be integrated by poly-poly
capacitor. The reason for such a huge filtering capacitor and small
ESR required by CFC is due to the large Dc loop gain (23kVN).
The performances of the LDRs using CFC and PCFC under
different load current and temperature are tabulated in Table 11.
Three load current levels and two operation temperature are in-
vestigated. At 27"C, as shown in Fig. 5, although the PM of the
loop response increases when the load current decreases, the UGF
decreases by more than one order of magnitude. It is a tradeoff be-
tween the stability and the speed of the loop response when using
CFC. However, from Fig. 6, both UGF and PM are steady under
three different load current levels when using PCFC. It is very clear
that LDR using PCFC provides much better performance under the
change of the load current.
When the operation temperature is increased to 70"C, it is as-
sumed that the ESR used by CFC is reduced to one-tenth of the
original value for simulating the temperature effect to the ESR [3].
From the results in Table 11, Fig. 7 and Fig. 8, PCFC provides
much steady stability than CFC. Thus, LDR using PCFC is nearly
insensitive to temperature variations.
Moreover, the LDR using PCFC always has larger UGF than
that using CFC under all load current levels and temperature. Thus,
PCFC not only provides absolute stability for LDRs under the
change of load current and temperature but it also improves the
speed of the loop response.
5. CONCLUSION
A novel frequency compensation technique PCFC for LDRs
has been presented and proved by simulation. PCFC improves the
stability of LDRs when the load current, temperature and ESR are
varying. As no large filtering capacitor is required, the whole LDR
including the filtering capacitor can be integrated into a single
chip. Moreover, PCFC provides faster loop response. Therefore,
it is well suited for LDRs inside low-voltage portable equipment
6. ACKNOWLEDGMENT
This work was supported by the RGC Competitive Earmarked
Research Grant, Hong Kong SAR Government, HKUST6007/97E.
'Austria Miko Systeme Group, Austria