New Robust 200mV Sub-threshold Full Adders

Xu Wang* , Weifeng He , Zhigang Mao

School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China * Email: {wangxu, heweifeng, maozhigang}@ic.sjtu.edu.cn Abstract In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The proposed full adders are employed in an 8-bit ripple carry adder and the simulation results exhibit 20% power saving and 34% Power-Delay Product (PDP) saving compared to typical CMOS adder. 1. Introduction Today, laptops, wireless sensor network nodes, medical electronics and other portable personal communication systems make explosive growth. However, the capacity of batteries cant meet the demand of the electronic products. Intensive work has been done in this realm and sub-threshold has been proved to be the most important low power design technique. In sub-threshold circuit, supply voltage is scaled down below the threshold voltage, the charging current is very small, and accordingly the speed is severely limited. Sub-threshold technology was originally used in analog circuit, and then some researchers paid attention to sub-threshold SRAM design. As the important and basic component in digital logic circuit, full adder has been designed in sub-threshold region recently. The CMOS full adder [1] is based on a regular CMOS structure with 28 transistors. The advantage is its robustness against voltage scaling and transistor sizing. In reference[2], an adder is separated into two XOR and one MUX, and four types of XOR gate are proposed: AP, BP, CP, DP. But extra inverters are needed, so they are not economical in area. Sense Energy-Recovery Full adder (SERF) uses only 10 transistors which is reported to be the best in power consumption, according to [3]. But such adder have a problem of threshold loss, the logic value 1 of the worst node is VDD-2Vth. Two new SERF adders are proposed in [4] and [5] (represented as new SERF and 14T in the following text) the threshold loss is improved to VDD-Vth. Complementary Pass-transistor Logic adder (CPL)[6] and 8T adder is proposed in [7], which use only 8 transistors, the least number of transistors, also have a problem of threshold loss. Transistor Function Adder (TFA), Transmission Gate Adder (TGA) have a problem of drivability. Hybrid adder[8] has good drivability and no threshold loss. In[9], Several sub-threshold full adder cells are proposed. These cells are designed with pass-transistor logic which means the source side of pass logic transistor network is connected to some input signals instead of the power lines. It is suitable for sub-threshold circuit. However these full adder cells are not robust, some could not work at 200mV in 0.18um process. The rest of the paper is organized as follows: In section II, these mentioned adders are compared, full adder cells in [9] are mainly introduced, and two improvements are suggested. In section III, 8-bit adders using these cells are introduced to verify the practicability. 2. 1-bit full adder cells A Full adder can be separated into three blocks, as shown in figure 1. Block 1 calculate P=A B, block 2 calculate Sum and block 3 calculate Carry out. In this way, the full adder becomes easier and more flexible.

Figure 1. Diagram of full adder In reference [7], authors give us four different structures of block 1, which is shown in figure 2, and three structures of block 2 as shown in figure 3, but only one structure of block 3 as shown in figure 4 (a). In this paper, we get two more structures of block 3, in figure 5 (b) and 4 (c). A full adder can be combined by selecting each structure from every three blocks which are named with three letters: the first letter refers to block 1, the second refers to block 2 and the last refers to block 3. For example, aba means the full adder is composed by block 1 (a) in figure 2, block 2 (b) in figure 3 and block 3 (a) in figure 4. In additional, the structure aba adder is TFA in [6].

978-1-4244-5798-4/10/$26.00 2010 IEEE

P P

Figure 2. Structures of block 1

Every PMOS transistors use the same ratio of W/L=1.5um/0.18um and every NMOS use the same ratio of W/L=0.36um/0.18um to make the compare impartial. Due to length of paper is limited, only some of simulation results are shown in table 1. Table 1. PDP of 1bit full adder cell Power( Delay(u PDP(pJ Transition Name nw) s) ) time(us) aba(TFA) 0.0379 9.9 0.37521 9 aaa 0.0453 8.5 0.38505 8 bba 0.0322 12 0.3864 10 bda 0.0318 12.4 0.39432 10 abc 0.0422 9.9 0.41778 5.4 adc 0.042 10.3 0.4326 6.8 aac 0.0497 8.9 0.44233 4 aca 0.0473 9.6 0.45408 8 TGA 0.0525 8.7 0.45675 9 acc 0.0516 10.1 0.52116 4 DP 0.0633 9.4 0.59502 15.1 CP 0.066 9.2 0.6072 13.8 CMOS 0.0496 14 0.6944 2.7 14T 0.0492 14.5 0.7134 13 Hybrid 0.0701 13.6 0.95336 2 CPL 0.097 9.9 0.9603 2.1 The structure aba (TFA) has the best PDP, and structure bda has best power consumption. The last letter are both a, that means they use block 3 (a) to calculate signal Co. Block 3 (a) show good performance, however, it uses transmission gate without a path to VDD or VSS, so the signal Co has not enough drivability, and if more adders are connect in series the signal will get weak. The last item in table 1 is transition time. It represent the time of a signals amplitude changing from 10% to 90% or from 90% to 10%. It reflect the drivability of a signal in a way and sometimes maybe include the effect of glitch. Structure aac, acc and abc have better transition time than the relative structure aaa, aca, aba (TFA), for example the transition time of structure aba (TFA) is 9us and the transition time of structure abc is 5.4us which is only 60% of structure aba (TFA). Block 3 (c) is more robust than block 3 (a). However, for the circuit block 3 (b) in figure 5, signal Sum is a input of block 3, so there is additional one transmission gates delay. Block 3 (b) has a little bigger delay and transition time than block 3 (c). In this simulation condition there are some structures can not work, because their internal nodes can not charge or discharge to sufficient voltage, they are 8T adder, 14T adder, SERF adder, structure bab, bca, bcb, cca and ccb. 3. 8-bit adders There are many type of multi-bit adder: ripple carry adder (RCA), carry select adder (CSA), carry look-ahead adder (CLA), parallel adder and so on. In sub-threshold

Figure 3. Structures of block 2

P

Figure 4. Structures of block 3

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P

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Figure 5. New structures of block 3

All these full adders including the adders introduced in section I are simulated with Spectre in 0.18um process at 50kHz and VDD equal to 200mV. Buffers are added before each input and a load capacitance of 1fF is added to each output to test adders in a more realistic condition.

region, RCA is welcome for its simplification and energy saving. So we use 8-bit RCA to verify the applicability of the proposed full adders. 8-bit RCA has a long delay because they are connected in series and the signal Ci is depended upon the former Co signal. So the frequency changes to 10kHz instead of 50kHz, and other simulation constrains are the same as 1-bit full adder cells in section II. Some simulation results are show in table 2. Structure bbb has best PDP, but transition time is 30us. It will not work when adding bigger load capacitance or using higher frequency. As the expectation, the block 3 (a) have bad performance because signal Ci is directly connected to Co with transmission gate. Three adders which are only different in block 3 are compared: the transition time of structure aaa is 63us, the transition time of structure aab is 6us and the transition time of structure aac is 4us.The proposed new structure block 3 (b) and block 3 (c), in figure 5, can provide stronger drivability. Considering both transition time and PDP, structure adc is the best with transition time equal to 7us, PDP equal to 6.09pJ, Power equal to 0.145nw and Delay equal to 42 us. It has 20% power saving and 34% PDP saving compared to typical CMOS adder. There are many adders cant work in this simulation constrains including structure aba (TFA), aca, ada, bab, bca, bda, caa, cba, cbb, cda, 8T adder, 14T adder , SERF adder, TGA, AP adder etc Table 2. PDP of 8 bit ripple carry adder Power(n Delay(u PDP(pJ Transition Name w) s) ) time(us) bbb 0.113 43 4.859 30 bdb 0.109 45 4.905 41 baa 0.133 43 5.719 58 abb 0.137 43 5.891 17 adb 0.134 45 6.03 17 adc 0.145 42 6.09 7 abc 0.148 42 6.216 7 aaa 0.152 42 6.384 63 cdb 0.133 52 6.916 27 aac 0.168 42 7.056 4 bcb 0.143 55 7.865 68 acc 0.179 44 7.876 4 BP 0.216 38 8.208 64 aab 0.169 54 9.126 6 CMOS 0.181 51 9.231 3 cab 0.158 63 9.954 32 CP 0.207 57 11.799 70 Hybrid 0.217 55 11.935 45 DP 0.214 62 13.268 84 CPL 0.331 45 14.895 39

4. Summary In sub-threshold region, leakage current becomes charging current, so some typical structures in CMOS design face some problems, for example having not enough drivability, threshold loss more energy and delay consumption. The improved structure with three state gate has stronger drivability and smaller delay. Among mentioned adders structure adc is best, which has 20% power saving and 34% PDP saving compared to typical CMOS adder, beside structure adc, structure abc, aac, acc are also suitable for sub-threshold circuit design. Acknowledgment This work was supported by the Hi-Tech Research and Development Program (863) of China under Grant No.2009AA011705. References [1] M. Alioto and G. Palumbo, Analysis and comparison of the full adder block, IEEE Trans. VLSI, p.806 (2002) 806823. [2] F Moradi, DT Wisland, TV Cao, A Peiravi and Hamid Mahmoodi, 1-Bit Sub Threshold Full Adders in 65nm CMOS Technology, IEEE International Conference on Microelectronics, p.268 (2008) [3] R. Shalem, E. John, and L. K. John, A novel low power energy recovery full adder cell, IEEE Great Lakes VLSI Symposium, p.380 (1999) [4] Farshad Moradi, Dag.T. Wisland and Hamid Mahmoodi, Ultra Low Power Full Adder Topologies, IEEE International Symposium on Circuits and Systems, P.3158 (2009) [5] T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy, A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem, Proceedings of World Academy of Science, Engineering and Technology volume 13, p.81 (2006) [6] R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass- transistor logic, IEEE J. Solid-State Circuits, p.1079 (1997) [7] Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy and Hiranmay Saha, A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates, International Journal of Electronics, Circuits and Systems, p.217 (2008) [8] K Navi, M Maeen and V Foroutan, A novel low-power full-adder cell for low voltage, Integration, the VLSI journal 42, p.457 (2009) [9] V. Moalemi, A.Afzali Koosha, Subthreshold 1-Bit Full Adder Cells in sub-100nm Technologies,Proc. Of the IEEE Computer Society Annual Symposium on VLSI, p.514 (2007)