IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO.

5, MAY 2007

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A 1.2 V Reactive-Feedback 3.110.6 GHz Low-Noise Amplier in 0.13 m CMOS

Michael T. Reiha, Student Member, IEEE, and John R. Long, Member, IEEE
AbstractA 15.1 dB gain, 2.1 dB (min.) noise gure low-noise amplier (LNA) fabricated in 0.13 m CMOS operates across the entire 3.110.6 GHz ultrawideband (UWB). Noise gure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise gure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87 mm2 IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples. Index TermsBias current-reuse, broadband amplier, low-noise amplier, monolithic transformer, reactive feedback, ultrawideband.

I. INTRODUCTION HE CHALLENGE of building a single RF front-end capable of receiving and processing a multiplicity of bands (e.g., for a software-dened radio) has stimulated interest in broadband RFIC design. This has arisen in response to the potential complexity, cost and power consumption of portable wireless devices designed to incorporate new wireless standards and applications, while maintaining backward compatibility with existing standards and capabilities. Concurrently, the potential of ultrawideband (UWB) radio for high data transfer rates (up to 1 Gb/s) within short distances ( 10 m) has also sparked research activity in broadband RF circuits and systems. Ultrawideband radio requires an integrated low-cost RF front-end with multi-GHz bandwidth, operating at the lowest power consumption and supply voltage. Scalability and compatibility with CMOS technology are essential for the analog/RF front-end circuits intended for this application. Broadband low-noise RF ampliers (LNAs) are therefore required for a multiband/multistandard RF front-end, UWB radio or perhaps both (e.g., a multiband/multistandard receiver with UWB capability). Reducing the number of LNAs by reducing the number of RF receive paths could drastically reduce power consumption, chip size, and cost in a multiband/multistandard radio. However, at present it is unclear how multiple antennas and preselect lter paths can best be multiplexed efciently to a single LNA input. Nevertheless, the wideband LNA must offer robust RF performance (i.e., gain and dynamic range) over many gigahertz of bandwidth with levels of current consumption comparable to existing narrowband ampliers.

Manuscript received September 18, 2006; revised January 17, 2007. This work was supported by Dutch STW Contract DCS-6422e. The authors are with the Electronics Research Laboratory/DIMES, Delft University of Technology, 2628 CD Delft, The Netherlands (e-mail: m.t.reiha@tudelft.nl; j.r.long@tudelft.nl). Digital Object Identier 10.1109/JSSC.2007.894329

When considering short-range, high bit-rate wireless communication using ultrawideband technology, two competing standards: multiband orthogonal frequency division multiplexing (MB-OFDM) and impulse-based direct sequence code division multiple access (DS-CDMA) have been proposed for standardization [1], [2]. However, different bands proposed for North America (3.14.8 GHz), Europe (68.5 GHz) and Japan (3.44.8 GHz, 7.2510.25 GHz) complicate the pursuit of a low-cost, generic design, unless the design encompasses all regional bands with adaptivity controla corollary to the challenge of building a multiband/multistandard LNA as described in the preceding paragraphs. A truly integrated solution requires that the ultrawideband LNA operate under low power conditions (10 mW, or less), taking advantage of the reduced component count while conforming to the relatively low UWB transmit power density ( 41.3 dBm/MHz) permitted by regulatory agencies (e.g., the FCC in the US). Implementation in a digital CMOS process allows complete integration of the analog/RF front-end with back-end digital signal processing (DSP) circuitry, which are performance and cost-sensitive blocks for both software-dened radio and impulse-based UWB radio. However, the supply voltage must be constrained to approximately 1 V when designing into the latest deep-submicron CMOS technologies. Important specications for the LNA include input power matching, low noise gure and distortion, power gain and minimum gain variation. However, unlike narrowband circuits, these specications must be consistent and satised over the entire frequency range, which is 3.110.6 GHz for operation in all regions of the world. A broadband LNA designed for fullband UWB radio (both standards), but also potentially applicable to a multiband/multistandard receiver, is presented in this paper. The LNA is implemented in a 0.13 m CMOS process and operates from a 1.2 V supply to demonstrate compatibility with a single-battery integrated radio. Bias current-reuse enables multistage RF performance with single-stage DC power consumption. A noise gure on the order of 2 dB as well as broadband gain and port matching without a lossy multistage input lter, is achieved through the use of reactive-feedback via on-chip transformers. Results referenced to both on-wafer probe tip and wirebond at the LNA input demonstrate the circuits viability in a packaged environment. Section II of the paper begins by outlining the tradeoff between gain and bandwidth within the context of current state-ofthe-art amplier topologies relevant to broadband LNA design [3], and specic to UWB applications [4][7]. Reactive-feedback is introduced as a means of lowering the LNA noise gure while still operating under low power conditions as demon-

0018-9200/$25.00 2007 IEEE

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Fig. 2. Resistive-feedback RF preamplier.

Fig. 1. UWB LNA using cascode gain cell, input lter, and output buffer [4][6].

strated in [8] and [9]. Section III discusses the circuit design details of the two-stage reactive-feedback LNA, while Section IV presents and discusses measurement results and compares measured performance to representative samples taken from the current literature. II. BROADBAND AMPLIFIERS This section reviews the state-of-the-art broadband and UWB low-noise ampliers, and outlines the advantages with respect to power consumption and noise performance of a reactive feedback topology. A two-stage cascaded LNA employing local reactive feedback networks and a current-reuse scheme is introduced as a low-power, low-noise, moderate-gain solution. A. Theoretical Limitations Bode proposed that the gain and bandwidth of a single amplifying device cannot be simultaneously increased beyond a limit product. [10], parameterized as the gain-bandwidth A consequence of a xed gain-bandwidth product is that feedback can be used to trade off gain and bandwidth to realize a (e.g., of a transistor) is directly prodesired result. portional to DC power consumption, hence, improving while constraining DC power consumption can be a formidable task when designing a high-performance amplier in an advanced technology. B. UWB LNA Designs Recently reported LNAs designed for the 3.110.6 GHz UWB have been implemented in both feedback [3], [7] and non-feedback congurations [4][6]. The designs described in [4][6] are adaptations of narrowband LNAs, which use a cascode core and a multistage input lter for broadband matching of the core amplier to a 50 source (see Fig. 1). However, the input lter insertion loss degrades the ampliers noise gure, and this loss must be compensated for by increasing the gain,

thereby lowering bandwidth. The cascode gain-cell provides isolation between the input and output ports. The transistor cascode and low-Q (broadband) inductively-peaked resistor at in Fig. 1) constrain the DC headroom and the drain ( limit the allowable bias current when operating for a 11.2 V supply. A gain of 810 dB requires a wide FET for sufcient on the order of 250 m in 0.18 m transconductance (e.g., technology) [4]. An additional compromise in this design is used as a low the source follower output buffer output impedance (i.e., 50 ) interface. The follower consumes additional DC power (e.g., 5 mA [4]) and constrains dynamic range, bandwidth, and interfacing to a mixer stage. An alternate approach to the modied cascode is a negative-feedback amplier. Feedback offers numerous benets for broadband amplication, including gain, stability over processing and supply variations, lower distortion (at the cost of gain), and the ability to tailor port impedances for noise and impedance matching. The resistive-feedback (i.e., transimpedance) amplier of Fig. 2 is a xture in optical receiver design where high transimpedance, low input-referred noise and at-group delay are achieved at the expense of power consumption. However, the difculty in simultaneously achieving a 50 input match, low noise gure and low power consumption makes such a simple feedback stage unsuitable for a UWB LNA. Achieving a broadband input match by increasing the ) increases the input referred noise feedback (i.e., lowering from both the feedback loop and the load. Improving the loop ) improves gain at a constant current level (i.e., increasing required for a 50 input the noise gure by increasing the match, at the cost of increased distortion and lowered supply headroom. The increase in distortion may be compensated for by increasing the supply voltage, however, this is counterproductive when attempting to implement a low-power UWB amplier. Attempting to increase the loop gain by increasing the transistor transconductance requires a larger FET gate area that , ). Parasitic results in greater overlap capacitance (i.e., capacitances restrict the bandwidth around the feedback loop, reducing both the input and output pole frequencies. Peaking or other frequency compensation techniques are then needed to compensate for the bandwidth limitations. The resistive-feedback LNA implemented in 90 nm CMOS recently reported in [3] uses shunt-shunt feedback around a

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Fig. 3. gm-enhanced cascode LNA employing broadband source follower feedback [3].

-enhanced cascode stage to achieve a voltage gain of 23.5 dB and a minimum noise gure of 2.5 dB. A simplied schematic of this LNA is shown in Fig. 3. Feedback via a source-follower buffer ( - ) preserves the loop-gain, while an additional source-follower ( - ) is used to drive the following (mixer or output) stage. Performance is limited by the source followers, which restrict the overall dynamic range and bandwidth. DC power consumed by the followers as well as the amount of feedback (e.g., feedback resistor value) must also be traded off with power consumption and noise performance. C. Reactive Feedback LNA As previously mentioned, negative feedback allows a designer to exchange gain for bandwidth, which is useful when designing a UWB amplier. The reactive-feedback amplier of shown in Fig. 4 has a closed-loop transconductance

Fig. 4. Reactive feedback RF amplier (transconductance) stage. (a) Schematic. (b) Small-signal equivalent circuit.

(1) where is the forward current gain from gate to source of the ) FET (with gate-source impedance, (2) The open-loop transconductance is (3) where is the source impedance (typically 50 ) and is the input impedance [see (4)]. In the following analysis, the broadband transformer model of Fig. 4(b) (i.e., winding inductances are assumed large; ux leakage and parasitic capacitance from (1) is the inverse is neglected) is used. Feedback factor where is of the transformers effective turns ratio (i.e., the magnetic coupling factor and is the physical turns ratio),

which simplies to for the model of Fig. 4(b). Parasitic resistances in both the primary and secondary windings ( and , respectively) are retained in order to relate the physical size of the transformer to both the noise gure and input impedance. Feedback via the Miller capacitance is neglected, and the transconductance predicted by (1) is assumed valid . for frequencies away from the pole frequency is neglected The drain-induced gate noise of transistor because the circuit is operating broadband and driven by a low impedance source [11], thereby simplifying the noise analysis. As the open-loop gain increases (i.e., increasing in (1)), the approaches the reciprocal closed-loop transconductance of the feedback factor (i.e., ). This makes the stage gain independent of DC biasing (including selection of load, ) and transistor sizing. Thus, increasing the loop gain to establish a 50 input impedance to match an antenna does not imply an increase in the supply voltage. The input impedance computed from the small-signal equivalent circuit of Fig. 4(b) is approximately given by

(4) It depends chiey on the feedback factor and transistor . Also, increasing the closed-loop gain transconductance while maintaining a 50 input impedance requires an increase

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Fig. 5. Schematic of the two-stage broadband LNA in CMOS.

in , resulting in either excessive current consumption or poor bandwidth due to a large area FET. The input impedance predicted by (4) is independent of the drain impedance because drain-gate feedback is ignored in the analysis. However, as the drain impedance rises, feedback via the drain-gate overlap caaffects the input and the approximation of (4) pacitance of no longer holds. Using the small-signal equivalent circuit in Fig. 4(b), the noise factor can be expressed as

(5)

where . The noise contributions and are scaled relative to the noise of from resistances the source resistance by the transformer (i.e., scaling ). Of the terms dependant on the channel noise in by dominates the noise (5), the term directly proportional to factor when driven by a high-impedance source, while the term dominates when driven by a lowinversely proportional to impedance source. Ignoring and assuming a low-impedance source (e.g., 50 antenna), one can see from (5) that increasing the feedback factor reduces the effect of channel noise on . The transconductance also has a strong effect on the drain current noise contribution in this case. However, increasing transconductance via device sizing to reduce the noise factor has less impact on the bandwidth of a reactive versus resistive feedback amplier, as will be explained in the following sections. D. Two-Stage LNA Topology With Reactive Feedback The two-stage modied-cascade amplier shown in Fig. 5 can achieve higher gain than a single cascode. Each stage inand , ) to stabilize forcorporates local feedback (via ward gain over the full UWB range of 311 GHz. Losses in the transformer are minimized in an effort to reduce the overall noise gure, which is dominated by the input stage. Feedback

at the output reduces the output and input impedances of the second gain stage, creating an impedance mismatch between the two stages that results in a broadband signal transfer [12]. DC bias current is recycled through both stages under a single supply voltage (i.e., the cascaded gain stages are biased as a cascode), thereby providing a higher gain-bandwidth product with less lower current and power consumption [13]. is biased through the feedback winding of Transistor where the gate voltage is decoupled on-chip by capac. The input feedback via is used to set the input itor impedance close to 50 over a wide bandwidth. RF current generated by is sensed by the primary winding of connected in series with the transistor source, and a fraction is fed back to the secondary winding thereby lowering the input impedance. The current sensing, current feedback network does . not compromise the (desired) high output impedance of is an on-chip RF choke that conducts DC bias current to while blocking RF signals. Beyond the selffrom and resonant frequency of the bias network formed by , the impedance at the drain of is lowered, thereby improving the circuits isolation from potential out-of-band interferers at higher frequencies. The interstage RF path is AC into autotransformer . The output coupled via capacitor voltage of the second transimpedance stage is sensed and loop to lower both a current is fed back through the . the output as well as the loaded input impedance seen by The transimpedance second stage also eliminates the need for a low-Q (i.e., broadband) output load or matching network used in [4][7], thereby simplifying the output interface without driving up power consumption. The second stage consumes as much current as the main amplier for sufcient loop gain to transform the output impedance properly. Stability over the entire ultrawideband places additional constraints on the transistor sizing, and DC biasing. The reactive-feedback loop around the output stage lowers the second-stage input impedance while compensating for inter-stage attenuation losses. Negligible DC losses with reactive feedback also allows the circuit to operate under a low supply voltagefurther reducing the DC power consumption while allowing operation from a single 1.2 V supply that can be shared with digital baseband circuitry. Interfacing the LNA to the mixer stage could be accomplished by replacing the off-chip bias-tee of Fig. 5 with an on-chip inductor and MIM capacitor. However, the coil required for the bias choke would require additional chip-area. An alternative, is to AC couple the LNA directly to a mixer quad (i.e., mixer in cascode with the LNA output), which shares bias current between the mixer and LNA. This retains the advantage of low overall power consumption, but requires a larger supply voltage. In many applications the RF power amplier and baseband analog signal processing circuits also run from a higher supply voltage than 1.2 V (e.g., 2.7 V), making this a viable alternative. III. CIRCUIT DESIGN RF design of the AC-cascade, DC-cascode LNA topology requires implementation of a low-loss, broadband inter-stage bias network. The rst (input) amplier stage is designed for moderate current gain, low noise gure and a 50 input impedance

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matching over the 311 GHz band using a high magnetic coupling feedback transformer. The second stage also uses a high magnetic coupling autotransformer to broaden the frequency response of the overall LNA. A. DC Bias and RF Inter-Stage Design A current-reuse scheme allows the two-stage cascade amplier of Fig. 5 to be biased as a cascode as described previously in Section II. Transistors , are equally sized at 126 0.13 m and are intended to divide the 1.2 V supply equally across the two transistors. The bias current is controlled , which is supplied externally by the gate voltage of and de-coupled to ground on-chip via 11 pF backend metal ca. Similarly, the source of is grounded by 13 pF pacitor metal-insulator-metal (MIM) decoupling capacitor, . The does not reduce the supply ohmic drop at DC across headroom signicantly under low bias current. Hence, it is sized to be as large as the technology will allow (i.e., 5.5 turn, 4.6 nH, 14 GHz) in order to cover the full ultrawideband without a resonance occurring in the bias network. Note that a larger contributes more shunt parasitics to the interstage RF path. The MIM decoupling capacitor (11 pF) is symmetric in layout, so that its terminal parasitics are equally distributed. B. Input Stage The input stage is used to provide low-noise, broadband input matching with enough gain to realize a noise gure of 2 dB. The initial design of the input stage (neglecting bandpass frequenof cies of UWB) is an iterative procedure that balances the and the effective turns ratio of for a suitable 50 match. As seen in (4), the feedback factor (approximately the inverse of the effective turns ratio) and transconductance of dominate the broadband input impedance when the rst-stage current gain is sufciently large. A DC bias current of 7.5 mA was chosen for the amplier so that the overall DC power consumption is 9 mW. Thus, the required transconductance is governed primarily by the aspect . Turns ratio can be selected with either low or ratio of high magnetic coupling (i.e., low or high -factor). Low magnetic coupling requires fewer physical turns in the transformer layout, a smaller form factor, and arguably introduces lower substrate parasitics. However, poor magnetic coupling between windings makes the circuit susceptible to processing variations or cross-coupling from other passive structures and on-chip circuitry. Moreover, the 3 dB bandwidth of the transformer is dened by the magnetic coupling factor between the windings [14]. High magnetic coupling and low ohmic losses in the feedback transformer are also used to ensure that the broadband noise gure [refer to (5)] is kept close to 2 dB. In the case of a 1:1 transformer with equal input and output resistive loading (neglecting capacitive shunt parasitics of the windings), the minimum magnetic coupling factor is (6) in order to establish a 3 dB bandwidth of bandwidth of 311 GHz, the coupling factor . For a 0.57 predicted

Fig. 6. Even-odd mode analysis of 1:1 simplied transformer with inverting transformer connection.

Fig. 7. First amplier stage (on-wafer version) showing cutaway of transformer.

by (6) is rather relaxed. Improving the accuracy of this model (see Fig. 6) by adding equal capacitive loading to both windings increases the minimal coupling to (7) which results in a 0.84 for a 3 dB bandwidth of . Both low and high cut-off frequencies may be determined through respective odd mode and even mode excitations, where (8)

The 50% increase in coupling predicted by the model including capacitive parasitics, suggests that a transformer should be designed with the highest -factor possible in order to achieve full-bandwidth and minimum attenuation through minimization of the shunt parasitic capacitances. Fig. 7 illustrates the input stage design of the LNA designed specically for on-wafer testing. The transformer windings are placed in an overlay conguration, which realizes the greatest coupling (i.e., both magnetic and electric). The RF input signal enters the innermost winding and couples to the adjacent turn. This creates a positively-coupled T-section where the leakage and therefore helps to inductance appears in series with

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peak the overall response. Effectively, this allows a larger magnetizing inductance, which shifts the lower 3 dB cut-off frequency and broadens the overall response. The gate tie-down for transistor prevents gate oxide failure during diode the backend manufacturing process. It is connected in parallel , and de-coupling capacitor with the gate biasing source . Connecting the gate tie-down diode to the cold side of the transformer winding (i.e., an RF ground) reduces the parasitic capacitance at the gate of , thereby reducing passband attenuation and allowing greater exibility in transistor and transformer sizing. The high frequency roll-off in the ampliers response is primarily determined by the shunt parasitic capacitance at the RF input to the substrate in combination with the . For a higher cut-off frequency, the gate-drain parasitic of current amplier stage should drive a very low-impedance load, which in this case is the input of the second stage. Equally important is the lower cut-off ( 3 dB) frequency, which is determined by the secondary self and mutual inductances when driven by a 50 source. After selecting a bias current for low-power, the following design methodology was used to design the rst stage. The input device is rst sized as a compromise between gain-band, transconductance efciency , width product and minimum noise gure. For a given width, the device layout is optimized initially for low noise by choosing the number of gate ngers and the width of each nger to minimize the parasitic resistance of the polysilicon gate. The FET size selected in the design has a total width of 126 m using 63 2 m FETs in parallel. Once the transistor aspect ratio has been selected, the device transconductance is xed for a given choice of bias current (in this case 7.5 mA). Knowing the transconductance, the turns ratio of the input transformer required to set the input impedance to 50 is determined [e.g., from (4)]. For this design, an overlay is used. The transformer with a coupling factor, transformer magnetizing inductance is selected so that so that the lower cut-off frequency of the rst stage is slightly above 3 GHz (i.e., lower edge of the LNA passband). Increasing the magnetizing inductance increases the overall chip area of the transformer. The transformer frequency response is optimized by aligning the winding connected to the transistor source (i.e., the primary winding) directly beneath the secondary winding connected at the transistor gate. In this way the primary shields the secondary from the conductive substrate [15]. Effectively, this peaks the high-frequency response of the rst stage at the expense of increased interwinding capacitance that decreases the midband gain and reduces the lower cut-off frequency in magnitude (i.e., (i.e., used in the greater bandwidth). The input transformer, on-wafer version) has a physical turns ratio of 4.5:1, an approximate low-frequency magnetic coupling of 0.85, and occupies 185 180 m of chip area. The primary and secondary are 0.26 nH and 3.2 nH, respectively. self-inductances of C. Second (Transimpedance) Stage The rst-stage output drives a low input-impedance transimpedance stage ( 18 at 3 GHz), in order to widen the

Fig. 8. (a) Modied transimpedance amplier. (b) Normalized transimpedance versus normalized frequency with variable magnetic coupling. (Normalized meaning relative to the response (i.e., midband transimpedance and 3 dB cut-off frequency) where L = 0.) .

amplier passband and mitigate the Miller effect for the input ). The rst stage is modelled by current source, stage (i.e., , as shown in Fig. 8(a). Output impedance, although small ( 172 at 3 GHz), is modelled by capacitor which also includes parasitics from the interstage choke and MIM coupling models the input capacitance of the capacitor. Capacitor cell with interstage parasitics. Feedfortransconductance ward around the cell (i.e., via of an nMOS transistor) is neglected in order to simplify the following analysis. With a load impedance of 50 and running at a small bias current (i.e., power constraint of 9 mW for the LNA), the loop-gain must be improved by increasing the aspect ratio of the FET. The parasitics of the transistor load the second-stage input and constrain the upper end of the frequency response. The feedback provides shunt peaking, while the inductance inductance in series with the second-stage input will separate the parasitic capacitance of the driving source from the amplier input capacitance as illustrated in Fig. 8(a). Two separate inductors would complicate the physical layout and consume substantial chip area. Winding the two inductors together as a transformer with positive magnetic coupling between the windings facilitates series peaking of the overall frequency response. It can be seen that increasing the magnetic coupling between the windings [see Fig. 8(b)] enhances the bandwidth (to increase loop gain) while not requiring an increase in that would dissipate additional DC power. An overlay 4:3.5 turn transformer conguration, similar to the rst-stage transformer design, is used in the second stage ( in Fig. 5) to realize high 0.86 while reducing the overall chip magnetic coupling area consumed by the physical implementation.

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Fig. 9. Chip micrograph of the UWB LNA (on-wafer version).

D. Implementation Considerations Two LNA versions were designed in the IBM-8RF-DM 85 GHz and both occupy 0.13 m CMOS technology 0.87 mm of area (on-wafer version shown in Fig. 9). One amplier is intended for on-wafer characterization, while the second is intended for bondwire interconnection to a printed circuit board. The RF input signal enters the input-stage transformer via a 50 transmission line. RF attenuation at the input is minimized by utilizing thick-metal transmission lines so that there is minimal effect upon the noise gure. Low-Vt devices ( 0.36 V) [16] allow the LNA to operate over the fullband at varying power levels for adaptability. The input and output RF signal pads are 50 m 75 m in area and add a parasitic capacitance of 37 fF.

Fig. 10. (a) Test xture enclosing LNA. (b) PCB-LNA wire bonding arrangement.

IV. MEASUREMENT RESULTS On-chip measurements are from wafer probing of rst-pass silicon without de-embedding. Packaged measurements were rst obtained from a test-xture which encloses a double-sided, copper-clad PCB as shown in Fig. 10(a). The chip is mounted to the PCB and wirebonded to the input/output 50 CPW feedlines as seen in Fig. 10(b). The bondwire interconnect length is 200250 m, resulting in a series inductance to the RF input/ output of approximately 0.25 nH. The results measured for the packaged LNA are de-embedded and referenced to the PCB/ bondwire interface (i.e., not the IC bondpad). A. Summary of Results gain and isolaThe measured and simulated 50 are plotted in Fig. 11. UWB band limits are shown tion by the dashed vertical lines. The on-wafer and packaged gain

measurements are 15.1 dB ( 1.4 dB variation1) and 15.3 dB ( 2.2 dB variation), respectively. The high-frequency roll-off in gain (consistent in both versions) could be reduced by reducing the second-stage transformers interwinding capacitance, which above 9 GHz. degrades the series peaking of for both on-wafer and Minimum measured isolation packaged versions is 28.1 dB and 30.4 dB, respectively, and improve beyond the loaded self-resonance frequency of ( 14 GHz). Unlike traditional feedback ampliers, the LNA isolation is not compromised as the feedback loop around the input stage is separated from the interstage node and the output . port by The noise gure over a broad bandwidth, as shown in Fig. 12, demonstrates the effectiveness of reactive feedback. On-wafer minimum noise gure (NF) is 2.1 dB at 6 GHz, while its variation over the 311 GHz is limited to approximately 0.86 dB. In contrast, the minimum NF for the packaged version is 2.04 dB at 5 GHz, while the variation over the 311 GHz is 0.94 dB. The
1dened as the difference between maximum and minimum values over bandwidth of interest.

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Fig. 13. Gain and noise gure versus frequency at various DC bias levels. Fig. 11. Gain and isolation of the feedback UWB LNAs versus frequency.

Fig. 14. Input reection coefcient of the UWB LNAs versus frequency. Fig. 12. Noise gure of the UWB LNAs versus frequency.

difference in measured NF is greater beyond 7 GHz, and can be attributed to the increased resistance of the input bondwire. On-wafer gain and noise gure measurements at DC bias levels of 6 mW, 9 mW, and 11.6 mW (respectively) are illustrated in Fig. 13. Variation in both gain and noise gure are consistent over their respective bandwidth, at approximately 1.4 dB and 0.5 dB. Decoupling the amplier loop-gain from the DC power dissipation as a result of reactive feedback allows the amplier to operate at different bias levels with minimal bandwidth reduction. This could be an attractive feature for adaptive radio systems. Excellent input matching across the band is also realized in both measured cases. Fig. 14 depicts the input matching controlled by feedback transformer and the loop gain of the rst stage. The lower frequency limit is determined by the size of s magnetizing inductance in combination with the system

impedance (i.e., 50 .). Stray inductance due to imperfect coupling (in the on-wafer version) and bond-wire inductance (in the packaged version) further degrades the lower cut-off frequency. feedforward impedance and parThe combination of the asitic capacitances shunting determine the high-frequency dB over the limit. On-wafer measurements show range from 2.210.6 GHz with nulls of 44 dB and 38 dB at 4.4 GHz and 5.8 GHz, respectively. Packaged measurements 9 dB over (referenced at the bondwire interface) show 10 dB in the the range from 2.1910.49 GHz, while range of 3.4510.38 GHz. Fig. 15 illustrates the output matching. Broadband stadB across the entire range. bility is achieved with Without a buffer stage, on-chip matching relies primarily provided by and . The null on feedback around (on-wafer version) is 32 dB while the seen in the range for 10 dB is 38.1 GHz. The minimum

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TABLE I MEASURED PERFORMANCE SUMMARY AND COMPARISON

Fig. 16. LNA (on-wafer version) group delay with S versus frequency.

phase as reference

Fig. 15. Output reection coefcient for the UWB LNAs versus frequency.

of 30.8 dB in the packaged version occurs at 4.67 GHz, 10 dB for 74.7% of the range between while 3.397.65 GHz. The output match is poorer than the input match, however, the LNA output impedance in an integrated design is not constrained to 50 . The objective in this design is to demonstrate that a broadband output interface is attainable without compromising low-power consumption. The LNA group delay (refer to Fig. 16) measures the amount of phase distortion (i.e., pulse spreading in the time domain) and is of particular interest for impulse radio implementations like DS-CDMA. On-wafer minimum group delay coincides with the . Beyond this null, the average delay is 81 ps rst null of

with maximum and minimum values of 104 ps and 52.1 ps, respectively. Both measured (on-wafer) and simulated curves are approximate in value and concavity with an approximate range of 75130 ps over the full UWB. The origin of the two anomalies is unknown but is understood by observing the reduced at these frequencies. slope of Table I compares the performance of the prototype ampliers with state-of-the-art designs reported in the recent literature. The third-order input intercept IIP measurement range of 48 GHz for the on-wafer LNA was limited by the broadband power splitter/combiners used for the two-tone test. Both linearity results are consistent with what is expected from narrowband designs. The IIP may be improved by either increasing the supply voltage or bias current, which has worked for the bipolar LNA listed in the table [5], but not in the case of the resistive feedback LNA [3].

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B. Note on RF Input Protection From ESD As mentioned in Section III-B, electrostatic discharge (ESD) protection is implemented at the RF input by connecting diode to the ground-side of the transformer winding (i.e., the secondary winding in Fig. 5). The clamp diode used on the proand decoupling catotype is designed to protect input FET pacitor from destructive charging effects during manufacturing (i.e., the antenna effect when plasma-etching metals). However, this small area diode clamp is not designed to protect the RF input from failure due to an ESD event which may occur in handling of the LNA chip or in manufacturing of an RF sub-assembly. Failure analysis of a number of samples indicates that the robustness of the LNA input to such ESD events could be improved if clamping devices capable of handling the required and ground transient currents were connected between (i.e., replacing the clamp diode in Fig. 5). A reverse-biased diode to clamp negative-going transients combined with a supply bus clamp for positive going transient protection, is one possible implementation. This arrangement is similar to a recently-reported ESD implementation, which uses an on-chip inductor to separate the capacitive loading effects of ESD clamp devices from the RF signal path for a 90 nm CMOS LNA [17]. We have attempted to calibrate the level of ESD robustness that could be expected from such an implementation. First, the LNA was tested by applying a 100 ns pulse at the input using the transmission line pulse (TLP) method of ESD stress testing [17] with grounded. As expected, the input fails consistently when the breakdown voltage of the gate oxide for the input FET is exceeded (i.e., above 6.3 V). A second TLP test was then performed between the RF input pad (refer to Fig. 5). Gate oxide catastrophic failure and the occurs at 6.3 V, corresponding to 1.8 A of input current. Assuming a source impedance of 1.5 k (as in the human body model, HBM), this current corresponds to an HBM voltage level of 1.8 A 1.5 k , or 2.7 kV at failure. Adding margin to account for the ON-state resistance of the on-chip ESD clamps and their 0.5 V turn-on voltage, it is estimated that the 2 kV level of ESD protection (HBM test) could be realized for the wideband reactive-feedback LNA. Conrmation of this estimate requires testing of a revised prototype, but these preliminary results encourage further investigation.

and 311 GHz, respectively. A second LNA, mounted and bonded to a PCB and biased under identical conditions, has a measured gain of 15.3 2.2 dB and a noise gure of 2.51 0.47 dB over the aforementioned ranges. In addition to stabilizing the gain and NF over a wideband, the on-chip reactive feedback networks enable broadband input/output matching in a 50 environment, obviating the need for an input matching lter and power-consuming output buffers.

ACKNOWLEDGMENT The authors gratefully acknowledge technical support provided by W. Straver of the ERL/DIMES Laboratory at TU Delft. Technology access was facilitated by J. Pekarik and D. Harame of IBM Microelectronics, Burlington, VT. J. Li and R. Gauthier, also of IBM, Burlington, coordinated the ESD testing. Fabrication was facilitated by MOSIS.

REFERENCES
[1] R. Aiello et al., Multi-Band OFDM Physical Layer Proposal Update, IEEE 802.15-03/449r2-TG3a, Nov. 2003. [2] R. Fischer et al., Merger #2 Proposal DS-CDMA, IEEE 802.15-03/ 334r5-TG3a, Nov. 2003. [3] J.-H. C. Zhan and S. S. Taylor, A 5 GHz resistive-feedback CMOS LNA for low-cost multi-standard applications, in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 200201. [4] A. Bevilacqua and A. M. Niknejad, An ultrawideband CMOS lownoise amplier for 3.110.6-GHz wireless receivers, IEEE J. SolidState Circuits, vol. 39, no. 12, pp. 22592268, Dec. 2004. [5] A. Ismail and A. A. Abidi, A 310-GHz low-noise amplier with wideband LC-ladder matching network, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 22692277, Dec. 2004. [6] F. Lee and A. Chandrakasan, A BiCMOS ultra-wideband 3.110.6-GHz front-end, IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 17841790, Aug. 2006. [7] Y. Lu, R. Krithivasan, W.-M. L. Kuo, and J. D. Cressler, A 1.83.1 dB noise gure (310 GHz) SiGe HBT LNA for UWB applications, in Proc. IEEE RFIC Symp., San Francisco, CA, 2006, pp. 5962. [8] D. Cassan and J. R. Long, A 1 V transformer-feedback low noise amplier for 56 GHz WLAN in 0.18 m CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 427435, Mar. 2003. [9] M. T. Reiha, J. R. Long, and J. J. Pekarik, A 1.2 V reactive-feedback 3.110.6 GHz ultrawideband low-noise amplier in 0.13 m CMOS, in Proc. IEEE RFIC Symp., San Francisco, CA, 2006, pp. 4144. [10] H. W. Bode, Network Analysis and Feedback Amplier Design. New York: Van Nostrand, 1945. [11] E. H. Nordholt, Design of High-Performance Negative-Feedback Ampliers. Amsterdam, The Netherlands: Elsevier, 1983. [12] E. M. Cherry and D. E. Hooper, Amplifying Devices and Low-Pass Amplier Design. New York: Wiley, 1968. [13] F. Bonn, A low current high performance LNA for global positioning receiver applications, in Proc. IEEE MTT-S Symp. Technologies for Wireless Applications, Vancouver, BC, Canada, Feb. 1995, pp. 113115. [14] J. R. Long, Monolithic transformers for silicon RF IC design, IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 13681382, Sep. 2000. [15] T. S. D. Cheung and J. R. Long, Shielded passive devices for siliconbased monolithic microwave and millimeter-wave integrated circuits, IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 11831200, May 2006. [16] Foundry technologies 130-nm CMOS and RF CMOS, IBM Corp., IBM Product Brief, 2003. [17] D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, A 5-GHz fully integrated ESD-protected low-noise amplier in 90-nm RF CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 14341442, Jul. 2005.

V. CONCLUSION A reactive-feedback LNA topology, implemented in 0.13 m CMOS technology and intended for 3.110.6 GHz UWB was demonstrated. The reactive-feedback networks, implemented via on-chip transformers allow the LNA to operate under a low (i.e., digital) supply voltage of 1.2 V. An interstage bias network allows the two-stage cascade amplier to be DC biased as a cascode, thus re-using bias current between stages resulting in a total dissipation of just 9 mW of DC power. An LNA designed for on-wafer probing demonstrated a gain of 15.1 1.4 dB and a noise gure of 2.5 0.43 dB over the ranges 3.110.6 GHz

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Michael T. Reiha (S03) received the B.A.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2002, and the M.Sc. degree in electrical engineering from the University of Michigan, Ann Arbor, in 2003. Currently, he is pursuing the Ph.D. degree at the Delft University of Technology, The Netherlands, where his research interests include high-speed and broadband amplier IC design. Mr. Reiha was the recipient of the Best Student Paper Award from the 2006 IEEE RFIC Symposium.

of Technology, Delft, The Netherlands, in January 2002 as Chair of the Electronics Research Laboratory. His current research interests include low-power transceiver circuitry for highly integrated radio applications, and electronics design for high-speed data communications systems. Prof. Long is currently serving on the Technical Program Committees of the IEEE International Solid-State Circuits Conference (ISSCC), the European Solid-State Circuits Conference (ESSCIRC), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), and GAAS2004 (EuMW). He is a former Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received the NSERC Doctoral Prize and Douglas R. Colton and Governor Generals Medals for research excellence, and Best Paper Awards from ISSCC 2000 and IEEE BCTM 2003.

John R. Long (S77M83) received the B.Sc. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 1984, and the M.Eng. and Ph.D. degrees in Electronics Engineering from Carleton University, Ottawa, ON, Canada, in 1992 and 1996, respectively. He was employed for ten years by Bell-Northern Research, Ottawa (now Nortel Networks) involved in the design of ASICs for Gb/s ber-optic transmission systems and for ve years at the University of Toronto. He joined the faculty at the Delft University