Reg. No.
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Question Paper Code : 22014
B.E. / B.TECH. DEGREE EXAMINATIONS, MAY / JUNE 2025
Sixth Semester
Electronics and Communication Engineering
19EC603 – VLSI DESIGN
(Regulations: Mepco – R2019)
Duration: 3 Hours Max. : 100 Marks
Answer ALL Questions
BTL, CO
PART A – (10 2 = 20 Marks)
R, CO1 1. The condition for saturation is ___________. Justify your answer.
A) Vgs = Vds B) Vds = Vgs – Vt
C) Vgs = Vds – Vt D) Vds greater than Vgs – Vt
U, CO1 2. Which one of the following processes is preferred for the gate dielectric (SiO2) of
MOSFETs? Justify your answer.
A) Sputtering B) Molecular Beam Epitaxy C) Dry oxidation D) None of these
A, CO2 3. The NMOS & PMOS transistor are used to produce ___________ respectively.
Justify your answer.
A) Strong ‘0’ & Strong ‘1’ B) Degraded ‘0’ & Degraded ‘1’
C) Strong ‘1’ & Degraded ‘0’ D) Strong ‘0’ & Degraded ‘1’
A, CO2 4. Which of the following vector part selection is considered ILLEGAL for the given
example: wire [7:0] bus; reg [31:0] virtual_add;? Justify your answer.
A) bus[5] B) bus[1:0] C) virtual_add[5:0] D) virtual_add(0)
A, CO3 5. For the circuit shown in the figure, P and Q are the inputs and Y is the output. The
logic implemented by the circuit is? Justify your answer.
A) NAND B) NOR C) XOR D) XNOR
R, CO1 6. Outline the flow chart of VLSI design process.
A, CO3 7. Construct a logic circuit for one/zero detection with minimum logic effort.
R, CO4 8. Why transparent latch based systems are called as clock skew tolerant systems?
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R, CO4 9. Identify the need for refreshing circuits in dynamic RAM cells.
R, CO5 10. Define the terms Controllability and Observability.
PART B – (5 16 = 80 Marks)
A, CO1 11. a) i. Examine the DC transfer characteristics of CMOS inverter and
analyze the relationship between the input and output voltages in its
five different regions of operation. (12 Marks)
A, CO1 11. a) ii. Apply CMOS logic to build the circuit for the expression
Y= (A+B)CD and sketch the stick diagram. (4 Marks)
OR
L, CO1 11. b) i. Analyze MOS transistor non-ideal behavior based on the following
parameters.
A) Channel Length Modulation
B) Temperature and Geometry Dependance
C) Velocity saturation & mobility degradation
D) Body effect (12 Marks)
U, CO1 11. b) ii. Explain the significance of photolithography process in manufacturing
IC using CMOS technologies. (4 Marks)
U, CO2 12. a) i. Explain in detail about RC delay estimation with suitable examples. (8 Marks)
A, CO2 12. a) ii. Develop a Verilog code for 4 bit parity generator and checker in data
flow modeling and also give suitable test benches for checking its
functionality. (8 Marks)
OR
U, CO2 12. b) i. Distinguish Static and Dynamic power dissipation along with power
reduction techniques. (8 Marks)
A, CO2 12. b) ii. Develop a Verilog code for a 1 to 4 demultiplexer and perform
functional verification by applying suitable test benches. (8 Marks)
U, CO3 13. a) Make use of the timing diagram to illustrate the minimum delay and
maximum delay constraints in flip-flops and latches. (16 Marks)
OR
L, CO3 13. b) i. Model a CMOS circuit for XOR gate using CMOS logic and Pseudo
nMOS logic. Compare their merits and demerits. (8 Marks)
U,CO3 13. b) ii. Interpret how do synchronizers help in communication between
asynchronous clock domains, and why are they important for
preventing data corruption in digital systems? (8 Marks)
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E, CO4 14. a) Compare and contrast the memory read and write operations of
SRAM structures by assigning suitable values to bitline and wordline
of 6T SRAM cell and DRAM cell. (16 Marks)
OR
U, CO4 14. b) i. Illustrate the working of Pseudo-nMOS NAND ROM with suitable
diagrams. (8 Marks)
U, CO4 14. b) ii. Interpret how Content Addressable Memory (CAM) is commonly
used in a Translational Look-Aside Buffer (TLB), and what role does
it play in improving memory address translation? (8 Marks)
U, CO5 15. a) i. Briefly describe the concepts of BIST and IDDQ testing. (12 Marks)
U, CO5 15. a) ii. Explain in detail about the stuck-at- Fault model. (4 Marks)
OR
U, CO5 15. b) Explain the various components involved in the Boundary Scan Test
in detail, providing necessary diagrams to support your explanation. (16 Marks)
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