Reg. No.

Question Paper Code : 19695

B.E. / B.TECH. DEGREE EXAMINATIONS, MAY / JUNE 2023

Sixth Semester
B.E. – Electronics and Communication Engineering
19EC603 – VLSI DESIGN
(Regulations: Mepco – R2019)
Duration: 3 Hours Max. : 100 Marks
Answer ALL Questions

BTL, CO PART A – (10  2 = 20 Marks)

R, CO1 1. What is Channel length Modulation?
U, CO1 2. Assume VDD = 1.8 V and the threshold voltage Vth = 0.4 V in the given circuit.
Estimate the voltage at nodes x and y with justification.

A) 1.8 V and 0.4 V B) 1.4 V and 1 V

C) 1.8 V and 1 V D) 1.4 V and 0.4 V
U, CO2 3. Write a Verilog program for 2:1 MUX using conditional statements.
U, CO2 4. The logical effort of the 3-input NOR gate is __________. Justify your answer.
A) 4/3 B) 5/3 C) 9/3 D) 7/3
U, CO3 5. What is the size of PMOS and NMOS respectively in the HI-Skew inverter?
Justify your answer.
A) 2 and 1/2 B) 2 and 1 C) 1 and 2 D) 1 and 1
R, CO3 6. What is clock skew?
U, CO4 7. What is the advantage of SRAM over DRAM?
R, CO4 8. Queue allows the data to be read and written on the principles of __________.
Justify your answer.
A) Last-In-First Out B) First-In-First Out
C) First-In-Last Out D) None of the above
U, CO5 9. What is the test vector for SA0 at the output of the NOR gate? Justify your
answer.
A) (1, 1) B) (1, 0) C) (0, 1) D) (0, 0)
R, CO5 10. What is Fault coverage?

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 PART B – (5  16 = 80 Marks)
U, CO1 11. a) i. Discuss the operation of the nMOS transistor and derive the
current equation for all the regions of operation. (8 Marks)
L, CO1 11. a) ii. Analyze the DC transfer characteristics of an inverter in different
regions of operation. (8 Marks)
OR
U, CO1 11. b) i. Explain the Fabrication steps of the CMOS inverter using N-Well
Technology. (8 Marks)
L, CO1 11. b) ii. Draw a stick diagram for the given function: Y = (AB+CD)’ and
estimate the area. (8 Marks)

A, CO2 12. a) i. Sketch a 3-input NOR gate with transistor widths chosen to
achieve effective rise and fall resistance equal to that of a unit
inverter (R). Compute the rising and falling propagation delays (in
terms of R and C) of the NOR gate driving h identical NOR gates
using the Elmore delay model. If C = 2 fF/µm and R = 2.5 kΩ.µm
in a 180nm process, what is the delay of a fanout-of-3 NOR gate? (8 Marks)
U, CO2 12. a) ii. Explain the sources of static and dynamic power dissipation in
CMOS and various means of reducing it. (8 Marks)
OR
A, CO2 12. b) i. Estimate the minimum delay of the path from A to B in the given
figure and choose transistor sizes to achieve this delay. The initial
NAND2 gate may present a load of 8 λ of transistor width on the
input and the output load is equivalent to 45 λ of transistor width.

(8 Marks)
U, CO2 12. b) ii. Write a HDL program to construct a 4-bit Ripple Counter. (8 Marks)

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U, CO3 13. a) i. Calculate the minimum delay, in τ, to compute F = AB + CD
using static gates and AOI22 gates from Figure A and Figure B.
Each input can present a maximum of 20 λ of transistor width.
The output must drive a load equivalent to 100 λ of transistor
width.

Figure A Figure B (8 Marks)

U, CO3 13. a) ii. Explain the dynamic circuits and how the monotonicity problem
can be resolved by domino logic. (8 Marks)
OR
U, CO3 13. b) i. Compare the Min delay constraint for various sequencing methods
with a neat timing diagram. (8 Marks)
U, CO3 13. b) ii. Explain how the various latches and Flip-Flops have been built for
the modern CMOS process. (8 Marks)

U, CO4 14. a) Explain the operation of the DRAM cell with its sub-array
architecture and Column circuitry. (16 Marks)
OR
U, CO4 14. b) Explain the different types of Programmable ROMs and
Programmable logic arrays in detail. (16 Marks)

U, CO5 15. a) i. Explain the various manufacturing test principles used to screen
defective parts with appropriate examples.
(8 Marks)
U, CO5 15. a) ii. Find the minimum test patterns required to detect the stuck-at-0
and stuck-at-1 faults at all the below-mentioned nodes in the given
circuit.

(8 Marks)
OR
U, CO5 15. b) Explain the three approaches for Design For Testability (DFT)
with necessary examples. How it differs from Design For
Manufacturability (DFM)? (16 Marks)

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