EC52

USN 1 M S
(Autonomous Institute, Affiliated to VTU)
(Approved by AICTE, New Delhi & Govt. of Karnataka)
Accredited by NBA & NAAC with ‘A+’ Grade

SEMESTER END EXAMINATIONS – MARCH 2022

Program : B.E. : Electronics and Communication Engineering Semester : V
Course Name : CMOS VLSI Design Max. Marks : 100
Course Code : EC52 Duration : 3 Hrs

Instructions to the Candidates:

 Answer one full question from each unit.

UNIT- I
1. a) State Moore’s and Dennards scaling laws. CO1 (04)
b) Draw the cross section of CMOS inverter in N-Well process with all CO1 (08)
fabrication processing steps.
c) Differentiate between the 2 types of design rules. Mention the λ based CO1 (08)
design rules which determine the minimum sized P and NMOS
transistors with illustrations.

2. a) Find the Boolean expression for the given stick diagram as shown in CO1 (08)
Fig. 2(a) and also draw the CMOS Transistor equivalent for the same.

Fig. 2(a)
b) Discuss the steps in RTL Synthesis with a flow chart highlighting circuit CO1 (08)
and logic design, logic synthesis and floor planning.
c) For an NMOS transistor Vds = 0.5v, Vgs = 2v, Ids = 0.856 mA, CO1 (04)
L= 2 µm, µn = 215 cm2 /V-sec. Vtn = 1v .Determine the charges
induced in the channel.

UNIT – II
3. a) Derive the expression for the current flowing through a MOS transistor CO2 (06)
in linear region.
b) Draw the circuit and stick diagram for the function: F = . CO2 (06)
c) For a certain inverter design, VOH = 1.7 V, VIH = 1.5 V, VOL = 0.2 V and CO2 (08)
VIL = 0.5 V.
Calculate the following voltages:
i. NML
ii. NMH
iii. Size of intermediate/Forbidden region
iv. If VDD = 1.8 V, what is the logical high output range?

4. a) A pMOS transistor has W = 1.5 μm and L = 0.5 μm. Calculate the CO2 (08)
current (VTp = -0.6 V) when VDD = 2 V, hole mobility 25 cm 2/Vs, oxide
thickness is 10 nm, for (i) V SG = 2 V, VSD = 0 V (ii) VSG = 2 V VSD = 1 V
(iii) VSG = 2 V VSD = 2 V

b) Draw the circuit for positive edge triggered D-FF, and show the output CO2 (12)

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waveform of the master and slave latches for the following input:

UNIT – III
5. a) For a 16-bit Carry Lookahead adder, show the structure and the PG CO3 (10)
logic diagram.
b) For a 16-bit Kogge-Stone adder, show the PG logic diagram. CO3 (10)

6. a) For a 16-bit Carry Skip adder, show the structure and the PG logic CO3 (10)
diagram.
b) Explain the operation of Booth multipliers with an example. CO3 (10)

UNIT – IV
7. a) CO4 (12)

In the above circuit, size the critical path for minimum delay, using the
method of logical effort. Assume that the input capacitance is 1 unit
and output capacitance is 12 units.
b) In a new technology, pMOS mobility is three times lesser than nMOS CO4 (08)
mobility. Draw a unit inverter in this technology.

8. a) Using the Elmore delay model, calculate the worst case delays for a CO4 (08)
3-input NOR gate.
b) A load of 64 units is to be driven from unit inverters. Design an inverter CO4 (12)
chain that drives this load with least delay. Verify that delay is
minimum by adding one more stage to the buffer and calculating the
delay.

UNIT – V
9. a) Show the sizes and hence calculate the logical effort of a 3-input NAND CO5 (12)
gate in (i) Dynamic CMOS Logic (ii) pseudo NMOS logic.
b) Discuss setup time and hold time and their origin in sequential circuits. CO5 (08)

10. a) Order Static CMOS, Pseudo nMOS and Dynamic CMOS logic families in CO5 (12)
terms of (i) size (ii) delay and (iii) power consumption.
b) Discuss the following: CO5 (08)
i. Time borrowing
ii. Setup Time
iii. Hold Time
iv. Contamination delay.
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