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SW Design System Level Design HW Design Virtual Prototype Physical Prototype SoC in Silicon

System Integration

S y s te m -le v e l D e sig n

Specification Co-Simulation System Design HW/SW Partitioning Architecture Templates

A r c h ite c tu r e E x p lo r a tio n

Block-level Design

HW-SW Co-Verification
Co-Simulation Co-Emulation FPGA Prototyping

Programming

S W D e sig n

H W D e s ig n

Logic Simulation Logic Synthesis Back-end / Fabrication

Compilation Debugging RTOS

SoC Platform Processor FPGA Memory I/O

Methodology-Specific Libraries
Master/Slave Library, etc.

Layered Libraries
Verification Library Static Dataflow, etc.

Primitive Channels
Signal, Mutex, Semaphore, FIFO, etc.

SystemC

Core Language
Modules Ports Processes Interfaces Channels Events Event-driven simulation

Data Types
4-valued Logic type 4-valued Logic Vectors Bits and Bit Vectors Arbitrary Precision Integers Fixed-point types C++ user-defined types

C++ Language Standard

sc_main( )

SystemC Simulation Kernel

while processes ready .notify( ) immediate

Elaborate

sc_start( )

Initialize .notify(SC_ZERO _TIME) delayed

Evaluate Delta Cycle Update

Advance Time

Cleanup

.notify(t) timed

SystemC Model

Simulation

Refinement

Synthesis

Rest of Process

More Accurate Cycletimed

System Architectural Model Transaction Level Modeling Register Transfer Level

TLM

RTL

Functionality

Approximatetimed

TLM

TLM

Un-timed

SAM

TLM
More Accurate

Untimed

Approximatetimed

Cycletimed

Communication

System level model Explore algorithms Verify against specifications Refine

- Not synthesizable - Event driven - Abstract data types - Abstract communication - Untimed

Timed model Explore architectures Do performance analysis Partition hardware / software Software Refine Hardware - Synthesizable - Algorithmic description - I/O cycle accurate - Clocked - Synthesizable - Clocked - FSM - Event driven

RTOS

Behavioral level model Refine

Target code

RTL model

To synthesis

Design Specification

Design Partition

HDL Design

Simulation Verification

Synthesis

Place & Route

System Integration & Test

Behavieral

4 RTL

10 Gate

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Structural Description
1 Processor Memory Peripheral interface Registers, ALUs, etc. Logic netlist, schematic Hierarchical Modules and Primitive instantiations 2 3

Behavioral Description
Procedural Assignment

Algorithm Dataflow/ RTL Boolean algebra

Nonblocking assignment Continuous assignment

View

Cell geometry Photomask Layout Database

Physical Description

C/C++ Source Codes

Compiler

Assembly Programs

Assembler

Object Files

Static Library

Linker

Executable Program

Testbench
Reference Model Test vector Generator DUT

expected result

Postprocessor

test vector

actual result

Test Generator Agent Driver Scoreboard Assertions DUT Environment

Checker Monitor

Executable image

MEM

BFM

ISS Processor model in C

Cross-compiler Hardware model Application program Target dependent library Simulator ISS program

Processor RTL model

Reset of SoC model HDL simulator

Perpheral models

...

(a) Core model co-simulation environment Interface (BFM) Real chip Reset of SoC model HDL simulator (b) Real-chip driven co-simulation environment Native code C program Interface (BFM) Reset of SoC model HDL simulator (c) Native-code co-simulation environment ISS Interface (BFM) Reset of SoC model HDL simulator Perpheral models Perpheral models Perpheral models

...

...

...

(d) Integrated-ISS co-simulation environment ISS C program Interface (BFM) Reset of SoC model HDL simulator (e) Decoupled-ISS co-simulation environment
M uP
Network processor

... ... ...

...

...

...

Perpheral models

Interface (BFM)

...

Reset of SoC model HDL simulator

Perpheral models

Development board

(f) ICE-based co-simulation environment

...

top ahb_bfm_socket Read task PLI/VPI interface Write task

S o c k e t lib ra ry

S o c k e t lib ra ry

a h b _ ta sk s

Testing routine

BFM API

Designed IP AMBA AHB

socket

C program domain

HDL simulator domain

Server srv_open(...);

Client

srv_accept(...);

cli_connet(...);

socket_get(...);

socket_put(...);

Pre-defined message passing communication

socket_put(...);

socket_get(...);

socket_close(...);

SystemC

SystemVerilog top task

Application Program DPI Interface

ahb_read

. . .

DUT

ahb_write

sc_channel sc_simcontext* sc_get_curr_simcontext ( ); sc_module (const char* nm); // ...

fifo_if FIFO_read ( ); FIFO_read_nb ( ); // ...

payload_if

print ( );

FIFO FIFO_read ( ); FIFO_read_nb ( ); print ( ); // ...

sc_channel sc_simcontext* sc_get_curr_simcontext ( ); sc_module (const char* nm); // ...

semaphore_if get ( ); put ( ); // ...

payload_if

print ( );

Semaphore get ( ); put ( ); print ( ); // ...

Test Generator Agent Driver Scoreboard Assertions HW Component

task/function call SystemC FIFO channel virtual interface

Environment

Checker Monitor

Test

Environment 1

Environment 2

HW1

...

HW2

sc_module sc_simcontext* sc_get_curr_simcontext( ); sc_module(const char* nm) // ...

Gen_base rand_testvector( ); send_testvector( ); // ...

Env_base configure( ); wait_setup( ); report( ); // ...

Generator rand_testvector( ); send_testvector( ); configure( ); wait_setup( ); // ...

Test Generator Agent Driver Scoreboard Assertions HW Component

mailbox virtual interface

Environment

Checker Monitor

SystemC design unit task/function call

DUT

AMBA Signals

AHB Slave State Machine

Register File

ALU

...

...

SystemVerilog top
ahb_decoder
HADDR HWDATA HRDATA

ahb_bfm interface

ahb_default_ slave

ahb_ s2m

DUT

HW1 arbiter Master1

interface

decoder default slave

s2m

m2s

Master2 HW2

DUT