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=
] [
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log 20 ] [
ps PP
ps
N
EMIR
dB FoM
jitter gate
(2)
where EMIR is the amount of EMI reduction, N
gate
is the
normalized gate count of profile generator and PP
jitter
is the
peak to peak periodic jitter increased due to the SSCG. The
FoM of proposed modulation profile is better about 2.15 dB
than the others. The overall power consumption of the
proposed SSCG PLL is 61mW.
IV. CONCLUSION
In this paper, the sawtooth dual-tone modulation profile is
proposed and compared to the conventional triangular and
triangular dual-tone modulation profiles and a FoM is
TABLE I
COMPARISON OF VARIOUS MODULATION PROFILES FOR SSCG
Jitter
Modulation profile
Normalized gate count of profile
generator
EMI reduction
(RBW=1kHz)
[dB]
Peak to peak periodic jitter
increased due to SSCG [ps]
Random rms jitter
[ps]
Figure of Merit
[dB]
Triangular 1 20.3 6.2 8.0 24.75
Triangular dual-tone 2.77 24.2 5.5 8.1 24.74
Sawtooth dual-tone (proposed) 1.39 23.8 7.8 8.2 26.89
(a) (b)
(c) (d)
Fig. 5. Measured output spectrums of various modulation profiles : (a) without SSCG, (b) triangular modulation profile (c) triangular dual-tone
modulation profile (d) sawtooth dual-tone modulation profile.
846 IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, May 2010
introduced for fair comparison of various modulation profiles.
Experimental result shows that the proposed sawtooth dual-
tone modulation profile provides the 23.81 dB EMI reduction
with very slight increase in timing jitter. The EMI reduction is
comparable to that of the triangular dual-tone modulation
profile while the gate count of the modulation profile
generator of the proposed one is only half of that of the
triangular dual-tone modulation profile. Thus, the FoM of
proposed modulation profile is better 2.15 dB than the other
modulation profiles.
REFERENCES
[1] Serial ATA Workgroup, SATA : High speed Serialized AT Attachment,
Revision 1.0, 26, May, 2004.
[2] Design for EMI, Application Note AP-589, Intel, February 1999.
[3] K. B. Hardin, J. T. Fessler and D. R. Bush, Spread Spectrum Clock
Generation for the Reduction of Radiated Emissions, IEEE
International Symposium on Electro-magnetic Compatibility, pp.227-
231, Aug. 1994.
[4] W. T. Chen, J. C. Hsu, H. W. Lune and C. C. Su, A spread spectrum
clock generator for SATA-II, Circuits and Systems, 2005. ISCAS 2005.
IEEE International Symposium on, pp23-26, May. 2005.
[5] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong; A low-jitter 5000ppm
spread spectrum clock generator for multi-channel SATA transceiver in
0.18m CMOS, Solid-State Circuits Conference, 2005. Digest of
Technical Papers. ISSCC. 2005 IEEE International 10-10, pp162 - 163
Vol. 1, Feb. 2005.
[6] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T.
Hayasaka, T. Takahashi and J. Kasai, Spread-spectrum clock generator
for serial ATA using fractional PLL controlled by modulator with
level shifter, Solid-State Circuits Conference, 2005. Digest of Technical
Papers. ISSCC. 2005 IEEE International 10-10, pp160 - 161 Vol. 1Feb.
2005.
[7] D. S. Kim and D. K. Jeong, A Spread Spectrum Clock Generation PLL
with Dual-tone Modulation Profile, Dig. Tech. Papers, IEEE VLSI
Circuits Symp. pp.96-99, Jun. 2005.
BIOGRAPHIES
Jang-woo Lee (S05) received the B.S. and M.S. degrees
in electrical and computer engineering from Hanyang
University, Seoul, Korea in 2005 and 2007 respectively.
He is currently working toward the Ph.D. degree at
Hanyang University. His research interests include a
PLL/DLL and high speed interface circuit design
Hong-jung Kim received the B.S. and M.S. degrees in
electrical and computer engineering from Hanyang
University, Seoul, Korea in 2007 and 2009 respectively.
He is currently working at Hynix Semiconductor. His
research interests include a PLL/DLL and high speed
interface circuit design
Changsik Yoo (S92-M00) received the B.S. (with the
highest honor), M.S. and Ph.D. degrees from Seoul
National University, Seoul, Korea, in 1992, 1994, and
1998, respectively, all in electronics engineering. From
1998 to 1999, he was with Integrated Systems Laboratory
(IIS), Swiss Federal Institute of Technology (ETH),
Zurich, Switzerland, as a Member of Research Staff
working on CMOS RF circuits. From 1999 to 2002, he was with Samsung
Electronics, Hwasung, Korea. Since 2002, he has been an associate professor
of Hanyang University, Seoul, Korea. He is the winner or co-winner of several
technical awards including Samsung Best Paper Bronze Award in 2006
International SoC Design Conference, Silver Award in 2006 IDEC Chip
Design Contest, Best Paper Award in 2006 Silicon RF IC Workshop, and
Golden Prize for research achievement in the next generation DRAM design
from Samsung Electronics in 2002. He serves as a member of technical
committee of ISSCC and ESSCIRC. His main research interests include
CMOS RF transceiver design, mixed mode CMOS circuit design, and high
speed interface circuit design
J.-W. Lee et al.: Spread Spectrum Clock Generation for Reduced Electro-Magnetic Interference in Consumer Electronics Devices 847