## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

97.478

1.0 Prologue:

Convolutional codes, why should complicate our lives with them

People use to send voice waveforms in electrical form over a twisted pair of wires. These telephone voice signals had a bandwidth of 4KHz. If the channel polluted the signal with a bit of noise, the only thing that happened was that the conversation got a bit noisier. As technology developed, we digitized the voice signals 8000 samples per second (twice the highest frequency to prevent aliasing) and transmitted the bits. If noise corrupted a few bits, the corresponding sample value(s) would be slightly wrong or very wrong depending on whether the bad bits were near the most-significant-bit or least-significant-bit. But for the most part, the conversation sounded noisier, but were still discernible. Someone saying “cat” will not be thought to have said “dog,” and probably would not even be thought to have said “caught.” When people started to send data files rather than voice, corrupted bits became more important. Even one wrong bit could prevent a program from running properly. Say the noise in a channel was low enough for the probability of a bad bit to be 1x10-9 i.e. the chances of a bit being correct is 0.999999999 (nine 9’s). The chances of 1000 bits being all correct is 0.999999 (six 9’s) and the chances of 106 bits being all correct is 0.999 (three 9’s). A 1 megabyte file (8x106 bits) has almost a 1% chance of being corrupted. The reliability of the channel had to be improved. The probability of error can be reduced by transmitting more bits than needed to represent the information being sent, and convolving each bit with neighbouring bits so that if one transmitted bit got corrupted, enough information is carried by the neighbouring bits to make allow a good estimate of what the corrupted bit was. This approach of transforming a number of information bits into a larger number of transmitted bits to improve robustness is called channel coding, and the particular approach of convolving the bits to distribute the information is referred to as convolution coding. The ratio of information bits to transmitted bits is the code rate (less than 1) and the number of information bits over which the convolution takes place is the constraint length. For example, suppose you channel encoded a message using a convolution code. Suppose you transmitted 2 bits for every information bit (code rate=0.5) and used a constraint length of 3. Then the coder would send out 16 bits for every 8 bits of input, and each output pair would depend on the present and the past 2 input bits (constraint length =3). The output would come out at twice the input speed. Since information about each input bit is spread out over 6 transmitted bits, one can usually reconstruct the correct input even with some transmission errors.

Convolution channel encoder

00101101

a b

11 10 00 01 01 00

a 3 bits in the input stream generate 2 bits

**in the output stream.
**

b Take the most recent of these input bits

plus one new input bit and generate the next 2 output bits. Thus each input bit effects 6 output bits.

FIGURE 1

Authors, Fred Ma, John Knight

January 27, 1999

1

Convolution Codes

In a simplified way, this kind of redundancy is similar to running three computers for critical missions. If each computer has only 1% chance of making a mistake, the chance that all three will make a mistake is (0.01) 3=10-6 i.e. much less likely. Further if two computers agree, and one differs, the maximum likelihood is that one computer made a mistake, and the two remaining computers give the correct result. This fact can be used to make the most probably correct decision on what the answer should be e.g. don’t fire the nuclear missiles, it’s only a flock of geese. The need for coding became all the more important in the use of cellular phones. In this case, the “channel” is the propagation of radio waves between your cell phone and the base station. Just by turning your head while talking on the phone, you could suddenly block out a large portion of the transmitted signal. If you tried to keep your head still, a passing bus could change the pattern of bouncing radio waves arriving at your phone so that they add destructively, again giving a poor signal. In both cases, the SNR suddenly drops deeply and the bit error rate goes up dramatically. So the cellular environment is extremely unreliable. If you didn’t have lots of redundancy in the transmitted bits to boost reliability, chances are that digital cell phones would not be the success they are today (if anyone even saw fit to devise digital cellular systems in such a noisy environment). As an example, the first digital cell system, Digital Advance Mobile Phone Service (DAMPS) used convolution coding of rate 1/2 (i.e. double the information bit rate) and constraint length of 6. Current CDMA-based cell phones use spread-spectrum to combat the unreliably of the air interface, but still use convolution coding of rate 1/2 in the downlink and 1/3 in the uplink (constraint length 9). What CDMA is, is not part of this lab. You can ask the TA if you are curious.

**2.0 Example of Convolution Encoding
**

XOR Output u1 MUX Shift register Input information bit stream x

The constraint length is 3. The output is effected (constrained) by 3 bits. The present input bit and the two previous bits stored in the shift register. Day Todays Yester- before days yesterbit days bit bit

0 1

clock

Double speed output z

Output u2 XOR

FIGURE 2

This is a convolution encoder of code rate 1/2 This means for each bit that enters the shift register, there are two output bits. Here they are transmitted one after another. The output u1 = x(n)⊕ x(n-1)⊕x(n-2). Here x(n) is the present input bit, x(n-1) was the previous (yesterdays) bit, etc. The output u2= x(n)⊕ x(n-2). The inputs to the XORs can be written as binary vectors [1 1 1] and [1 0 1] are known as the generating vectors for the code.

Authors Fred Ma, John Knight

January 27, 1999

2

Thus the self loop at state A in the state graph becomes the horizontal line from A@t=n to A @t=n+1 in the trellis diagram. Make the them all go from states @ t=n to states @ t=n+1. B. and the next state will be 10 = B.0. C ending in A @ t=n+6.Convolution Codes 2. This line represents the possible states at time t=n (now). 1999 3 . the input x(n)=1 will shift right into x(n-1). = 1 ⊕ 0 =1 z=[u1. B. C.1. C and D are in a vertical line. B. Then add the transitions to the diagram. The complete trellis diagram extends past t=n+1 to as many time steps as are needed. Suppose the encoder is reset to state A=00. FIGURE 5 x=1/ z=10 NOTATION TRELLIS 0/00 1/1 1 0/ 11 input/output x/z A 1 input 0 input B A C FIGURE 4 0 B 1 /0 0 /1 0 C D t=n 1 0 /0 1/10 01 1/ D t=n+1 More Complete Trellis Diagram A 0/00 1 /1 1 1 0/ 1 A 0/00 1/1 1 0/ 11 A 0/00 1/1 1 0/ 11 A 0/00 1 /1 1 0/ 11 A 0/00 1 /1 1 11 0/ A 0/00 1 /1 1 0/ 11 A B C D t=n 0 B 1 /0 0 /1 0 C 0 B 1 /0 0 /1 0 C 0 1/0 0 /1 B 0 C 0 B 1 /0 0 /1 0 C 0 B 1 /0 0/1 0 C 0 B 1 /0 0 /1 0 C 1/ 1 0/0 1/10 Authors Fred Ma. squash the state diagram so A. Make time the horizontal axis. Then:State= 00 = A = [x(n-1). The state is the two bits in the shift register.1 The Encoder as a Finite-State Machine The correlation encoder can be described as a Mealy machine.u2]= 11 After the clock.x(n-2)] FIGURE 3 D=11 x=0 z=01 2. John Knight 0 1/ 1/ 01 1/ 0 1/ 0 1/ 01 01 1 1 1 0 /0 1 1/10 D t=n+1 D t=n+2 1 0 /0 1/10 D t=n+3 1 0 /0 1/10 D t=n+4 1 0 /0 1/10 D t=n+5 1 0 /0 1/10 D t=n+6 January 27.2 The Trellis Encoding Diagram To get the trellis diagram. Put another line of states to show the possible states at t=n+1.0. Assume shift register was reset to zero and the first data bit x(n) = 1. Also it passes through states A. By following the trellis one sees that the output is 11 10 00 01 01 11. x=1 z=11 x=0/ z=00 A=00 x=0 z=11 B=10 x=1/ z= 0 x=0/ z= 1 0 0 C=01 x=1 z=01 x = x(n) state = [x(n-1). state bit x(n-1)=0 will shift right into x(n-2).x(n-2)] Output z=[u1. and the input is 1. D.u2] u1 = x(n)⊕ x(n-1)⊕x(n-2) = 1 ⊕ 0⊕ 0 =1 u2 = x(n)⊕ x(n-2).0.1.

Clock cycle input bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 shift reg (state) 00 Output [u 1. Test benches are easier to write and use if they are synchronous. Problem: Draw the state graph for the above constraint length 4 encoder. John Knight January 27. #10 x=1. // Right shift 1 position end The test bench is not part of the circuit. This means they always send out signals slightly after the clock. reg [2:0] State. It also means a writing style with few #n delay. 1999 4 .u2] 2.. #20 x=0. #10 x=0. 2. 3. #10 x=1. Calculate the output bits and states when one encodes these bits using a code rate 1/2. Convert the hexadecimal number to binary (12 to 16 bits). Problem: Draw the circuit for an encoder which has: a code rate =1/2. initial begin #11 x=1. Convert them to hexadecimal and then binary (Matlab has a function dec2hex). Test Bench module clk reset x u1 u 2 ConvEncode module Poor FIGURE 6 Authors Fred Ma. . Use this as data for the encoder below.. One can code it following the standard finite-state machine model with three-bit states. • • • • • Problem: Encoding a number Take the last 4 digits in your student (the least significant digits). 1. generating vectors [1111] and [1011].3 First Exercise: A Convolution Encoder. constraint length 3 encoder with generating vectors [111] and [101]..4 First Lab: Design a Convolution Encoder in Verilog The constraint length 4 encoder circuit is a finite-state machine. It supplies the input signals and may compare output signals with those that are expected. always @(posedge clk) begin State <=State >> 1. . Tabulate how the state and output values change with each clock cycle. constraint length of 4. It is also a shift register.Convolution Codes 2. or as a shift register. and then the first three time steps of the trellis diagram for the above constraint length 4 encoder. Feed in the least significant bit first.. Also reset the shift register to 00 before you start. where the “0”means no connection to x(n-1).

Write and simulate a finite-state machine encoder for the constraint length 3 system. Using “<=” would make the first subscript “0” i. 1.1 A Synchronous Test Bench In a synchronous test bench. Write a synchronous test bench so the other two modules can be simulated. reg [8:1] data. clk.4. Related problems will appear on the examination. // The #1 makes x appear 1ns after the clock. integer I. you must have the test bench automatically compare your answer with the result you obtained from your student number. Note there are many things not included like reset. 1999 5 . I<=I+1. x <= data[0] which would be unknown. // Underscore has no meaning except // to visually space the bits. Authors Fred Ma. Also the TAs will ask other members of the group to explain the submissions they did not submit. 2. reg x. and the other to delay the input signal x so it’s changes are obviously past the clock edge. x<= #1 data[I]. 2. data[8:1]=8'b1010_1101.5 Lab and Problem Rules This is the first part of the Viterbi decoder design problem which will be done by a group of three persons. There are only two delays here. This will effect their mark as much as their submission. end // send in a new value of x every clock cycle always @(posedge clk) begin if (I==9) $finish. // The nonblocking symbol “<=” insure that any other clocked module uses the same x // and the same I as this procedure. the always procedure here should use blocking “=” signs. and not the updated x or I. The three are to be submitted together with the name of the person doing each part attached to the part. //Fill this with the data stream to be encoded. 3. thus it is clear in which cycle x changes. forever #5 clk=~clk. Unlike procedures for synthesis. One wants I to increment before it is used as a subscript for data. Write and simulate a shift-register based encoder for the constraint length 4 system.e. clk=0. the test signals are timed by @(posedge clk) statements rather than each having its own timing. John Knight January 27. module SyncTestBench. one to set the clock period. All members of the group are responsible for knowing how to do each exercise. The number of exercises is divisible by three so one person in each group does one-third of the exercises.Convolution Codes 2. end endmodule For the constraint length 2 system. initial begin I=1.

only for decoding the numbers are output\input. John Knight January 27. One must chose either 10 or 01. On the trellis diagram on the right.1 The Hamming Distance This distance is used to show how far apart two binary numbers are. 11/1) we now show input Hamming distance . At this time either transition looks equally likely.1. there are two choices leaving state A. It is clear one should make the transition from A ⇒B. At t=n+1 in state B. 1999 6 /1 01 /1 01 /1 01 /1 01 / 01 1 D t=n+1 /0 01 10/1 /0 01 10/1 /0 01 10/1 /0 01 10/1 /0 01 10/1 D t=n+6 FIGURE 8 A Hamming distance B 10 1 01 B C D t=n B 1 C D t=n+1 C D t=n+2 Instead of input/output (i. 3. one receives 11 11.1 Decoding Using the Trellis Diagram Consider a decoder that receives the transmitted signal 11 01 01 00 10 11 going from t=n to t=n+6. the next input 01 causes a 1 output and a change to state D. The number of positions that are different is the Hamming distance.0 Convolution Decoder The next part of the project will be to design a convolution decoder. Applying the Hamming Distance to Decoding Suppose the first four received bits have an error so instead of 11 01. but wait! Authors Fred Ma. Compare the bits in the same positions in the two numbers. The number in the box is the Hamming distance between the received input and the bits for the transition. Received 11 input A 00 2 11 0 A 11 The next input has an error.Convolution Codes 3. 1001001 and 1001010 are distance 2 apart (d=2). Assume the trellis was reset to state A (00) at the start. Trellis Diagram for Decoding (Receiving) Received 11 input Decoded 1 output 00/0 A 11 /1 0 11 / FIGURE 7 01 1 A 00/0 11 /1 11 /0 01 0 A 00/0 11 /1 11 /0 00 1 A 00/0 1/1 1 0 11 / 10 0 A 00/0 11 /1 11 /0 11 0 A 00/0 11 /1 11 /0 A B C D t=n /1 00 10 /0 B C B /1 00 10 /0 C D t=n+2 B /1 00 10 /0 C D t=n+3 B /1 00 10 /0 C D t=n+4 B /1 00 10 /0 C D t=n+5 1 B 00/ 10 /0 C /1 01 0 01/ 10/1 3. 11. One goes through the trellis as before. We will be developing the more involved “Viterbi decoder” to retrieve the information bits from the transmitted bits.e. So the first input. Note there are no 11 or 00 paths leaving state B. one for input 11 0 and the other for input 00 2 . Thus 11and 01 are distance 1 apart (d=1). gives a decoded output of 1 and takes the machine to state B. so both possible paths are at Hamming distance 1. It should succeed even in the presence of some corruption in the transmitted bits.

then d=0 for the path to state C. 1999 7 . Rinehart & Winston. John Knight January 27. Thus the most likely path is A ⇒B⇒D⇒C⇒B⇒C with a cumulative distance of 1. We will chose a path through the trellis based on the cumulative Hamming distance. Then the sum. Thus at t=n+1 the proper path was not obvious. and edges represent an output of 1).Convolution Codes Received 11 input A 00 2 11 0 A error 11 Trellis Diagram 01 FIGURE 9 00 00 0 10 00 1 11 1 11 1 11 A 1 A A A 11 0 11 0 A B C Outputs is 0 is 1 B 10 1 01 11 B 1 00 1 B 00 10 1 01 0 B 1 00 10 0 1 B B 10 1 C D t=n+1 C 0 10 01 C D t=n+3 C 10 0 C D t=n+5 C D t=n+6 1 D t=n+2 D t=n+4 01 10 1 1 At t=n+2. 1989 1 1 D t=n+3 +1 D t=n+4 3 0 Authors Fred Ma. B. Holt. At t=n+5. Modern Digital and Analog Communication Systems. The A 00 2 0 FIGURE 10 A A 1 A +1 1+ 1+ 0 A 0 B 3 1 3 1 A B C D B 1 B C D t=n+2 1+ 1+ 1 B C D t=n+1 0 C 0+ 1+ 1+ 1+ 4 1 4 1 B 0 1 1+ 1 C C D t=n+5 The sum of the Hamming distances is shown like 1 + 1 + 0 until this gets too messy. However if one starts from C one has d=1 for either the path to A or to B. which is the sum of the Hamming distances as one steps along a path through the trellis. the choice is clearer. References: Bernard Sklar. and the corresponding output data is 11010 (Recall trellis edges represent a receiver output of 0. one path has a total distance of 1 from the input data. if one starts from D. Digital Communications Fundamentals and Applications.P. The table below shows how the Hamming distances sum as one goes down various paths through the trellis diagram. at t=n+2. and the distance for the current step. are shown in a hexagon and a box like 2 1 others have a distance of 3 or 4.Lathe.

1999 8 . no path has a zero Hamming distance “H”. The other one can never be part of the most likely path. He noticed that if two paths merge to one state. This means that with the constraint length 3 (shift-register length 2) system in the previous examples only have to remember 4 paths. hence we will erase it. B 1 C 01 11 1 2 B 00 10 01 2 6 C 0 0 1 2 1 10 2 3 D D t=n+2 t=n+3 FIGURE 12 Authors Fred Ma. The boxes 2 show one step Hamming distance The hexagons 4 show “H”. the number of paths can get quite large. The larger “H” path can never be the most likely path. This means a decoding ASIC may take considerable storage. John Knight January 27. Viterbi developed an algorithm 1n 1967. the path length should go for the length of the message in order to get the true maximum likelihood path. even in the presence of errors. which allows the many paths to be discarded without tracking them to completion. However it turns out that path lengths of 4 to 5 times the constraint length can almost always give the best path. only the one with the smaller cumulative Hamming distance. more compact RAM type memory rather than the faster flip-flops.0 The Viterbi Decoder The decoding example shown above has to follow multiple paths through the trellis. such the cell phone ones with constraint lengths (shift-register lengths + 1) of 6 and 9. In theory.” need be remembered. Received 11 input A B C D t=n 00 2 11 0 A B error 01→11 00 2 4 A 11 0 2 At t=n Starting at state A. there are two possible paths. The next few pictures show how the decoder can pick out the best path. FIGURE 11 10 1 1 01 B 1 C D t=n+1 C D t=n+2 C State 4 Cumulative Hamming distance 2 Hamming distance for this step 00 Rec’d input to make this transition Output a 0 if this transition is used Output a 1 if this transition is used Received 11 input A B C D t=n 00 2 11 0 A B C D t=n+1 error 01→11 002 4 00 1 5 A 11 11 1 5 2 0 2 10 1 01 1 1 1 01 Going out to t=n+3 The paths temporarily double to 8 A There are two paths to each node. In general a constraint length K system will have to remember 2K-1 paths. “H.Convolution Codes 4. For larger decoders. and remember them for future decisions. One has a larger cumulative distance. the cumulative Hamming distance At t=n+1 There are 4 paths out to t=n+2 Since the input has an error. and one may have to use slower.

down from four at t=n+3. and the four lowest distance ones will be kept. This is all important information up to to t=n+3. Eight paths are created temporarily Again at each node. only the lowest cumulative Hammingdistance path can be part of the most likely path so four of the eight paths will again be eliminated. John Knight January 27. B C D t=n C 1 C D t=n+2 B B 10 2 11 1 2 00 01 4 C C 2 D t=n+3 0 01 10 2 1 0 2 D t=n+1 2 4 D t=n+4 Rec’d 11 input A 0 error 01→11 A B 1 FIGURE 15 01 A 2 2nd error 00→01 A 2 10 00 1 3 111 3 1 A B C 1 A 3 B C D t=n 2 B 2 B C 2 2 C D t=n+1 1 C 11 1 3 B 00 10 01 0 2 C 2 2 4 4 Entering t=n+5 Eight new paths are created. The second error has made four paths all with equal chances of being the most-likely paths (four paths with 2 ) But see what happens next. Rec’d 11 A B 2 error 01→11 A B 1 4 2 01 A 5 11 A 2 error 01 →11 A A 01 A 2 5 A 0 0 B 2 6 B B B 1 B 2 1 B C D t=n C 1 C D t=n+2 1 2 C D t=n+3 2nd error 00→01 C D t=n C 1 C D t=n+2 C D t=n+3 D t=n+1 3 D t=n+1 2 Rec’d 11 input A 0 error 01→11 A B 1 FIGURE 14 01 A B 00 A A 11 1 3 1 2 3 2 2 1 Entering t=n+4. 1999 9 .Convolution Codes FIGURE 13 Here just the cumulative Hamming distances are shown so it is easy to see which paths should be erased. Here the unneeded paths are eliminated. Authors Fred Ma. D t=n+2 3 D t=n+3 1 D 0 10 0 2 D t=n+4 t=n+5 Note path dies out. There are now only two most likely paths.

2 5 11 2 5 00 10 01 0 3 C Entering t=n+6 Note how the correlation has A continued to act. B and D. Pick one randomly. Follow the path back from C -> B-> A-> C-> B-> C-> D-> B-> A. The paths to C and D have H= 4 4 D t=n+1 D t=n+2 D t=n+3 D t=n+4 Retrieving the Original Message Rec’d 11 input A B 0 error 01→11 A B A B 01 2nd error 00→01 A B A B FIGURE 18 10 A B 11 A B 11 A B 10 4 A B 4 2 C C C C C C C C 4 C Common path D D D D D D D D D t=n+1 t=n+2 t=n+3 t=n+4 t=n t=n+6 t=n+7 t=n+8 t=n+5 Entering t=n+8: One can be fairly sure the best path at t=n+8 ends at state C.Convolution Codes Rec’d 11 input A B C D t=n 0 error 01→11 A B 1 01 A 2 2nd error 00→01 A 2 10 3 3 11 A 100 2 5 10 3 2 B 0 A B 2 B C 1 2 B 2 C 1 C D t=n+2 3 2 2 C D t=n+1 D t=n+3 D t=n+4 FIGURE 16 Since two paths have the same H C as they are enter C. t=n+5 t=n+6 Here we choose the one B⇒C. John Knight January 27. We are now down to one most likely B path. 1999 10 . Authors Fred Ma. No matter what state you start in at t=n+8. The most likely path ends at B and a close second at A. From the solid (for “0”)and dashed (for 1) lines along the path one can decode the probable original message as 11010010 (travelling t=n to t=n+8). all paths come together when you get back to t=n+3. Rec’d 11 input A B 0 error 01→11 A B 1 01 2nd error 00→01 A 2 2 FIGURE 17 10 3 3 11 A 3 11 A 100 2 5 10 2 3 2 B 3 A B 2 A B 2 A B B 2 C D t=n C 1 C 1 C 3 2 2 C 2 C C 01 0 11 2 5 B 00 0 1 01 1 4 C 1 1 4 3 10 1 4 D D D t=n+6 t=n+7 t=n+5 Entering t=n+7: The one best path is getting fairly clear. we have no way of telling which 1 3 1 2 D 0 10 1 3 D is the better path. Also follow the paths back from A.

with input and use the Hk from step b). HA HB HC and HD Fill in Figure 22 but put ' ' ' '.” then the code is unable to tell if one path is more likely than another. Pick one path at random. This has already been done for H A Only the better path is written here. each Hk. If two branches entering a state have equal “H. In psedocode the comments are often more important than the code.Convolution Codes As illustrated above. and HD. Psedocode This is Verilog in which the syntax is not critical. calculate and fill in the values of hij and hence the H k for t=n+9. Input =10 HA= HB= H C= H D= FIGURE 21 1= h HB=4 B = = h 00 h 10 = = h 01 HC=2 C HD=4 D h 01 = A B C D h00= h11= h01= h10= A HA= B HB= C H C= D H D= t=n+10 h10= t=n+8 Input =10 HA= HB= H C= H D= FIGURE 22 A B C D h00= h11= h01= h10= A H A'= H C + h11 = 3 ' B H B= ' C H C= ' D H D= t=n+11 t=n+9 t=n+10 c)For the 3rd partner: Start at t=n+10. The cumulative Hamming distances H at each trellis step are HA. FIGURE 19 4. for '. John Knight January 27. For example begin. If the input is 00. and C to B both use the symbol h00. calculate and fill in Figure 21. Problem: Using the algorithm A typical step in the trellis decoder is shown for your convenience. The Hamming distance for each edge are given subscripts matching the input which makes them 0. h00=0.1 Exercise 2: A Viterbi Decoder Design 1. If the input is 10 or 01. in an expression. Input = 00 HA=4 A FIGURE 20 HA A 0/00 h00 1/1 1 h 11 0/ A h1 1 HA HB 11 B C 0 0h 0 1/0 /1 0 0h B HB HC 10 HD 1 1h 0 0/0 1/10 h10 D 1/ C D HC 01 h 01 HD t=n t=n+1 h00= h1 11 A HA= B HB= C H C= D H D= t=n+9 a) For the first lab partner: Starting at t=n+8 with an input of 00. h00=1. b) For the 2nd lab partner: Starting at t=n+9 using the Hk from step a) and input 10. if the input is 11. It need only remember N*(number of states) bits plus some temporary storage for the Hamming distances. Authors Fred Ma. HC. Let the new Hk at t=n+11 be written with a prime i. HB. h 00=2. end and semicolons may be omitted if the meaning is clear to the reader. Thus the edge from A to A . as in Figure 20. 1999 11 . the Viterbi decoder can decode a convolution code for a message of N bits in the presence of some errors.e. as well as a number.

John Knight January 27. h10. could you say. b) Another team member should use Boolean algebra to calculate them as binary numbers. Problem: The flip-flop procedure. For part b) use reg /*wire*/ [1:0] h00. a) Use if statements to calculate the Hk' to be associated with the four states at t=n+1.. Write a procedure to clock the flip-flops and store the necessary data. decoded output. The Hamming distances associated with the eight trellis edges for this step are h00.. Let the two input bits In[1:0] be y. end 2'b01 : . x}) 2'b00 : begin h00=0. h11=2. h01. and don’t forget a reset. Use HAnext instead of HA' since Verilog cannot handle the later. 2 bits for 1 • Following a) color backward along each path in turn... back to 1 bit. a) Calculate these distances using a case statement: case ({y.e it clocks HA <= HAnext. Problem: Write pseudocode to update the Hk in going from step t=n to step t=n+1. Don’t put combinational logic in a flip-flop procedure. mentioned earlier. . d) If the decoder delays the signal by 12 to 15 clock cycles. How far back (t=n+?) would you have to go to have maximum confidence in what the original data bit was? In communications latency is the term for the time difference between the time the input signal was received and the output signal is sent out. 5. Problem: Write pseudocode to calculate the Hamming distances for one step.. h00[0] = y^x. h11. 3. else . if (HA+h00 < HC+h11) then HAnext= HA+h00. that experience has shown gives the most likely bit for almost all cases... State the latencies for both (i) and (ii). Test decoder encoder • Using what you learned in a). 1999 12 . 4. For example:HAnext = ..Convolution Codes 2. Using the paths in Figure 18. This procedure stores the data i. etc. Start at t=n+8. you will show for this example that if one traces back far enough it does not matter which path one follows. h01. what would the latency be in clock cycles? There are two answers for c): (i) The latency as observed for one typical data stream as shown in Figure 18. Example: h00[1] = y&x .. Problem: When is the output correct? Experience has shown that all backward paths converge into one if one traces them back 4 or 5 times the constraint length. (ii) The latency. with Bench confidence. would anyone care assuming: • The signal was a digitized phone conversation? Authors Fred Ma. what the original data bit was between t=n+3 and t=n+4? Why not? original data bit encoded.. HA + h00 . c) If a decoder had to wait until all paths converged before it had confidence it could send out a correct output.. At what time (t=n+?) do the paths all converge? b) Look at Figure 14 in which the ending time is t=n+4.x. a) Take a copy of Figure 18. start at each state in turn and color backwards until you reach t=n or until you hit previous coloring. Combinational logic in parts 2 and 3 calculated the D inputs for the flip-flops.

It gives no information about the data. Problem: How to backtrack Figure 23 is the same as Figure 18 except the numbers are all removed. what was the original data between t=n+2 and t=n+3? If it was in state B at t=n+3. what was the original data (before encoding) between t=n+2 and t=n+3? If it was in state A at t=n+3. John Knight January 27. what was the original data between t=n+2 and t=n+3? If it was in state D at t=n+3. a) Use Figure 24 only. Thus by looking at Figure 25 and only Figure 25 partner two at time t=n+8 should be able to tell what the original bit was between t=n+2 and t=n+3. data is 0 is 1 Trellis Diagram with no signal knowledge superimposed A A A A A A FIGURE 24 A B C D t=n+2 B ? C D t=n+3 B C D t=n+4 B C D t=n+5 B C D t=n+6 B C D t=n+7 B C D t=n+8 b) Figure 25 is the same as Figure 24 except some little squares have been drawn associated with each state in each time step. You may establish some conventions like a 1 in the state C box means . This information would allow lab partner two to back trace with no further information.Convolution Codes • The signal was a www page? • The signal was a digital TV signal? 6. However they must be independent of the data. Figure 23 shows paths... • Lab partner one should fill a minimum of information in each square. Authors Fred Ma. but when you trace back to the area between t=n+2 and t=n+3 you cannot tell from the figure what the data was. If the decoder was in state C at t=n+3. 1999 13 . It still contains enough information to trace back from t=n+8. what was the original data between t=n+2 and t=n+3? orig.. Retrieving the Original Message FIGURE 23 A B A B A B A B A B A B A B A B 4 A 4 B 2 C D t=n C D t=n+1 C D t=n+2 C D t=n+3 C D t=n+4 C D t=n+5 C D t=n+6 C D t=n+7 C D t=n+8 4 Figure 24 shows a trellis decoder only.

John Knight January 27. Describe the Verilog storage declaration for an array to hold the backtracking information. this path’s H of 2 could increase in the next few cycles and another path might get the lowest H. 1999 14 . starts at state C at t=n+8 with H=2. Backing up would take the path to B at t=n+7. Consider Figure 26. The edge is a solid line which seems to say the original data was 0. Thus we are sure the edge from D at t=n+2 to C at t=n+3 is on the most likely path and the original data between these two clock edges was 0 (a solid line is 0. input rec’d A B error 01→11 A B 1 FIGURE 26 11 0 01 2 2nd error 00→ 01 A 2 10 3 3 11 A B 3 11 A 2 10 A 100 1 4 11 4 B 4 A B A B 2 2 1 B C B 3 3 2 A B 2 2 2 C C C On best path for sure 1 C C C C 1 01 0 0 2 2 4 C 3 D 2 D 3 D 4 D D D D D D t=n+1 t=n+2 t=n+3 t=n+4 t=n+5 t=n t=n+6 t=n+7 t=n+8 One may not be sure which data bit is best at t=n+2. Authors Fred Ma. However if one goes back to t=n+2 and travels ahead in time. Trellis Diagram with no signal knowledge superimposed A A A A A A FIGURE 25 A B C D t=n+2 B ? C D t=n+3 B C D t=n+4 B C D t=n+5 B C D t=n+6 B C D t=n+7 B C D t=n+8 c) How many bits per step must be stored to allow for backtracking? d) Review how to write an array in Verilog. only the best path survives to t=n+8. a broken line is 1).Convolution Codes • Using the same figure (Fill in the boxes at t=n+3 if you have not done so already) partner three should be able to determine the original data bit between t=n+1 and t=n+2. Because of the convolution code.2 Extracting The Original Data. You should hand in the filled in Figure 25 and your list of conventions. However if one traces the paths forward from t=n+2. The others die out. One dimension of the array will be the latency. only paths that start at D make it all the way to t=n+8. 4. The path with the lowest cumulative Hamming distance H . Unfortunately we can’t be sure of this.

Convolution Codes This illustrates why we want to wait six (or usually more) cycles before sending out the output. However the minimum H path never stops so the “0” injected into it at t=n+2 appears at t=n+8 beside state C which has the minimum H= 2 path. t=n+3 If one is in state C. storing the data in flip-flops during each clock cycle. In state A it would be 0.1 between t=n+3 and n+4 is carried forward to be used at t=n+9 Rec’d input A B C D 2nd error 00→01 A 10 A 11 A 11 A 10 00 4 A 0B 1 1C 00 1D 1 t=n+4 0 0 B 1 B 0 B 0 B C 00 0 4 A 0 B 4 2 4 0 C 0 C 1 C 0 10 1 00 1 0 5 C 2 1 D 0 D 0 D 1 D 0 D 1 01 5 1 t=n+5 1 t=n+6 1 t=n+7 1 0 t=n+9 t=n+8 The data capture at t=n+3 is carried forward along the paths.1. They arrive at the output at t=n+8. but its position (the state it is associated with) changes. This is the same result one got in Figure 18 by tracing the path backwards. Rec’d 01 2nd error 00→01 input A 2 FIGURE 27 10 A A 11 A 11 A 10 A 0 B 0 B 0 B 0 B 0 B B C D t=n+2 0 1 0 1 00 1 4 A 0 111 4 B 10 output output best output output 2 1 C 0 C 0 C 0 C 0 C 0 0 2 C 1 0 D 1 D 0 D 0 D 0 D 01 2 0 4 3 D 1 1 t=n+4 1 t=n+5 1 1 0 t=n+6 t=n+7 t=n+8 At t=n+3. B. John Knight January 27. but because of errors one might be A. and in B or D it would be 1. one is probably in state C. or D. the decoded data between t=n+2 and t=n+3. here they all do except the best path. Most of the paths will die out. At each cycle the data in a path stays the same. Whenever a path disappears. We will carry these data bits forward through the paths in the trellis diagram. FIGURE 28: The 0. we can be confident that the “0” data at t=n+2 is the most likely. would be 0. another path forks. the flip-flop beside state C indicates there was a 0 in this path between t=n+2 and n+3. inserted in the four paths at t=n+3.0. but the data stored in the flip-flops is different. Note the selected trellis paths are the same as in the previous figure. if they don’t break. 1999 15 t=n+3 . Carrying the Path Forward Instead of Tracing Back Figure 27 shows how 4 bits. Authors Fred Ma. Many of these forward paths disappear. If we are at time t=n+8. can be sent from flip-flop to flip-flop down the paths one clock cycle at a time. At t=n+8.

1 data bits between t=n+4 and n+5 are injected into four paths at t=n+5. It turns out this data can time-share flipflops with the data in the previous figures . the bits travelling down them are different unless they coincide by accident.” thus one can permanently associate state A with “0. Although the paths look the same as in Figure 27.” Solid lines are 0 dashed lies are 1 Rec’d input A 10 A 11 A 11 A 10 4 FIGURE 29 Output will not come until t=n+10 A Note that both paths going into state A correspond B to a data bit of “0. The state and inputs at t=n+k control the mux which selects what will be clocked into the flip-flop at t=n+k+1. This is to show that no matter which path is discarded states A and C always receive a “0” and states B and D always receive a “1. Both possible paths coming into each state at t=n+5 are shown even though the Viterbi algorithm will discard one. Authors Fred Ma. Figure 29 shows another point.” D t=n+4 2nd error 00 →01 A A 00 B 11 C 00 1D 1 t=n+5 10 A 0 B 1 B 4 1 B 0 C 0 C 2 1 C 1 D 0 4 0 D D 1 t=n+6 1 t=n+7 0 t=n+8 FIGURE 30 Rec’d input A 01 11 A 11 A 10 4 A 0 B C 0 B 0 B 0 B 0 B 0 B 0 B 4 11 C 00 11 t=n+3 D 0 C 0 C 0 C 0 C 0 2 4 C 1 D 0 D 0 D 0 D 0 D D Useless ff t=n+2 1 t=n+4 1 t=n+5 1 t=n+6 1 t=n+7 0 t=n+8 Figure 30 is like Figure 27 except it gives a hint of how the path tracing might be done in hardware. However: a) There is no need to use flip-flops to store the initial constants which are always 0.1.” C Also state C can be associated with “0” and. This bits would travel down the paths and be avaliable for output at t=n+10.Convolution Codes Figure 28 shows the next cycle where the 0. The paths are made by multiplexers. Figure 29 shows the bits that would be injected at t=n+5. If those 4 bits are shifted right the first flip-flops become avaliable to hold data injected later.0. The outputs in Figure 28 can use the same flip-flops since they come one cycle later at t=n+9. This will turn out to be the same logic used to select the path with the lowest H . John Knight January 27.0.. b) The four bits injected at t=n+3 need only four flip-flops at any time. Figure 30 looks like it has 20 MUXs and 24 flip-flops just to forward 4 bits.1.1. For example the outputs in Figure 27 come at t=n+8. 1999 16 . B and D with “1.

At any given time only 4 flip-flops are in use for today’s input set. The data is collected between t=n+2 and n+3 Note it is always the same. and one extracts all the registers active at t=n+6. Go back to Figure 31 which shows data injected at three different time steps travelling down the paths. The top of Figure 31 has two more sections which were left out because the figure was too big already. and 4 more for the set before that. Since all the columns represent the same time step all the MUXes are set the same way in each column. t=n+5 t=n+6 t=n+7 t=n+8 t=n+9 t=n+10 In Figure 32. #1 #2 #3 #4 MUX control wire s 4 4 0 0 0 1 4 0 0 0 1 4 0 0 0 0 Sections 4 and 5 would be up here but are not shown. The others only show what is going to be stored later or what was stored earlier. 0 1 section 3 0 0 1 1 0 0 0 1 This shows how the data collected between t=n+2 and t=n+3 goes through the shift register. have the same control lines. This means that at t=n+6 one can erase all but the shaded flip-flops. To see what is in the shift register at any given time follow a common time down as was done for the shaded MUXs at t=n+6. The MUXs do not change the bits but only place them in the right path. 0 1 t=n+3 Data from t=n+3 to n+4 t=n+4 0 0 1 1 t=n+5 1 0 0 1 t=n+6 0 1 0 1 t=n+7 0 0 1 1 t=n+8 0 1 0 0 0 1 0 1 section 2 How the data collected during t=n+3 to n+4 goes through the shift register. The bottom MUXs all use wire #4. Here they are set for t=n+6. The top (state A) MUX in each section all use control wire #1. However 4 more are used for the previous set. t=n+4 Data from t=n+4 to n+5 t=n+5 0 0 1 1 t=n+6 1 0 0 1 t=n+7 1 0 0 1 t=n+8 1 0 1 1 t=n+9 1 1 0 0 0 1 0 1 section 1 How the data collected during t=n+5 to n+6 goes through the shift register. See Figure 32. Authors Fred Ma. To get Figure 32 from Figure 31. Thus at t=n+6 one can overlay the three sections of the figure and ignore components operating at any time except t=n+6. note that at say t=n+6 only one set of flip-flops and MUXs is active in each section. 1999 17 . thus only the shaded flip-flops are in use. The control for the MUXs is represented by the line running through them. John Knight January 27. one obtains Figure 32 FIGURE 31: To show three shift registers can be compacted into one Only 4 flip-flops in each section are active at say t=n+6. etc.Convolution Codes The complete circuit can be arranged as an unconventional shift register. four data bits start through the trellis paths in each clock cycle. Note all MUXs operating at a given time. This line is a cable and contains 4 wires. When the five sections are overlaid.

John Knight January 27. convSig[2:1]. output dataOut.HB.The 4 path edges selected at t=n+6 were made thicker. #2 for the next etc. //maybe input HA.3 Summary of Circuit up to Here Test Bench Signal Source Comparison with original signal (loopback) dataIn reset clk Top module Encoder serial_in Error generator Encoder dataOut serial_in_err Top module serial_in_err Decoder Serial-to Parallel convSig[2:1] Calc_Came_From_and_Ham_Dist input clk.HD. came_from[4:1]. Data_Carry_Forward input clk. Can you calculate the data in column (v)? Hypertext link to solution (Figure 44).Convolution Codes FIGURE 32 WARNING: This shows hardware at a single time. Column (iv) contains data injected at t=n+2 and one has to go back to Figure 17 to obtain it. Authors Fred Ma. reset. reset. 1999 18 . output dataOut.e wire #1 for the top row.HC. t=n+6 Column 4. The first three columns contain the data that can be taken from Figure 26. #1 #2 #3 #4 Control wires 4 4 A 4 A A A 4 A 4 A 0 B 0 B 1 B 0 B 1 B B 1 0 1 C D 0 C 0 C 0 C 1 C C 1 D 0 D 0 D 1 D D 1 1 1 0 t=n+6 t=n+6 t=n+6 t=n+6 t=n+6 (i) (ii) (iii) (iv) (v) Shift register structure. The flip-flops contain the data for t=n+6. All 5 MUXs in a row are controlled by the same input line. i.

If you read the theory (with or without fully understanding it) you will know it is really a carry forward. Later you might consider making it part of the loopback test so it can be used for testing in the field. Your final design will be for a rate=1/2. i. • Second. One can do this automatically in Verilog for some parameters. If a module will be over a page of code. First it will be done as a test bench so it is only useful during simulation. One simple test is a loopback test where the output is sent back to the input and the two compared. 2. 1999 19 .3 on page 18. For others it too much trouble. 1However make it bigger and show the arguments passed to all modules. Draw a block diagram somewhat like that of Section 4. There are other blocks or concepts coming: a) Normally the encoder and decoder are widely separated so they cannot run from a common clock. We like originality in block diagrams as long as you can give a reason for changes. [1111]. design a distinctive comment style like /*|Para|* comment on parameters *|Para|*/ which indicate code where there are parameters nearby which will need attention. l .478 and we will use a common clock for both. Write Verilog for the Decoder Top Module and Encoder Top Module (already done?) 3. John Knight January 27.Convolution Codes 4. It is now you need to know where you are going. try to divide it.See the latch_sig below. In your comments cross-reference all the modules that are effected by the parameters. constraint length=4. To save work you will want to parameterize your design. The serial_in signal changes at twice the clock rate. Let the serial_in bits be labelled s. You will probably use a transparent latch and two flip-flops in the module.[101] decoder. Other thing you can do to your circuit to aid testing will be considered later. What to do for the lab 1. d) The Error Generator block is necessary if you want to simulate to the error correction properties. b) Your initial design will be a rate=1/2.[1011] decoder. e. Which one works for synthesis? c) Considerable emphasis will be given to testing. This is to make it easy to check things by hand or from books.. constraint length=3. r. [111]. Decide how these bits will come out of a transparent-high latch. The decoder will have a clock recovery module.. Authors Fred Ma. However it will not be done until Exercise/Lab 3. a. find out the way to pass parameters in Verilog. • First. serial_in 1D C1 1D C1 Transparenthigh latch 1D C1 clk serial_in s latch_sig ConSig[1] ConSig[2] e s r s e i a r i l Waveforms for serial to parallel FIGURE 33 1. Design a serial to parallel module.4 Second Lab: Start of Convolution Decoder in Verilog At this point the lab is starting to switch from a lab to a project. The Path Trace block has been described in Exercise 2 as a back-trace. You should be able to recognize each blocks in the block diagram. This is beyond 97.

1999 20 . Consider the Error Generator. if(I>latncy) y<=#1 data[I-latncy]. Try to make it so there is an error every 16 time steps (every 32 serial_in bits) on average. At the start dataOut will be the bit corresponding to the present lowest H (cumulative Hamming distance) so the latency will be only that of the serial to parallel converter. (See Exercise 2. A random 5-bit number will be 01110 (or any single value) one time out of 32 on average. 5. Alternately you might try a pseudorandom generator as you did in 97.350. John Knight January 27. 3 A input 11 00 2 5 110 0 FIGURE 35 A came_from[0]=down 2 3 B 3 11 0 2 5 0 10 0 3 01 2 5 B came_from[1]=up C came_from[2]=up 2 C 2 D 01 1 3 t=now 10 1 3 D came_from[3]=down t=next step (now + 1) Then write a preliminary Data_carry_Forward module “stub” which has input declarations for these four signals but no code to do anything with them. Later you will want to add a latency of 4 to 5 times the constraint length. Calc_Nxt_State_and_Ham_Dist // send in a new x every clock cycle always @(posedge clk) begin if (I==9) $finish. reg [4:0] randy. end assign err=(y!=dataOut) FIGURE 34 7. 8. Add to the module to generate a four-bit signal called came_from. How do you write a latch in Verilog? Hints.Convolution Codes 4. Thus it would show whether the next state A came from the present A (up) or C (down). Write the Verilog code for the serial to parallel module. This should include a loopback test which compares the dataIn (x on the right) with dataOut. Verilog for the Test Bench to handle the decoder and the encoder. if (randy = = 4’b01110) serial_in_err<= ~serial_in. Write the Calculate Next State and Hamming Distance module. You will have a delay (latency) between dataIn and dataOut. These will be the MUX control signals to carry the data forward. Figure 35 shows these bits and their meaning. always @(clk) begin //Run at twice clock rate //randy gets the 5 lsb of $random randy <= $random. FIGURE 36 9. I<=I+1.) 6. came from a higher state or a lower state. These signals indicate whether the trellis lines leading back from the next states to the present-time-step states. x<= #1 data[I]. Authors Fred Ma. at least not yet. There is a lot about pseudorandom generators in the notes. This gives a new random integer every time it is called. see Figure 45. For the moment treat it like a test bench so you can use nonsynthesizable constructs like $random.

2. t=now.5 Third Exercise: Forward Tracing 1. John Knight January 27. 1999 21 . the vertical axis shows the circuit (space). The trellis diagram shows more than one time. In the circuit you will show the data at the flip-flop’s D inputs ready to be stored. and the circuit to implement the carry forward on the right.Convolution Codes 4. Boxes in the same row show the contents of the same four flip-flops. 3. You will likely show different data stored inside the flip-flop. Problem: Walk-through of the data carry forward algorithm Figure 39 and following show one step of the trellis on the left. The table shows how the “state” input bits shift through the flip-flops with time. Problem: Write pseudocode for Data_Carry_Forward module a) The latency will be a parameter which will effect this module and the loopback test. The “\” and “/” symbols at the bottom show the direction the mux inputs came from. In each time step the six muxs in a column have the same control signal. Write down how to do this. 4. You will fill in the data as it exists in the circuit following the trellis. You will want to define this parameter from the top module (or maybe the testbench) and pass it down. Problem: Assign a group member to clean up unfinished parts from Lab 2.1 Feed Forward. an Alternate Viewpoint time D C B A n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 “State” Inputs 0 1 0 1 1010 1010 1100 1010 1010 1100 1100 1111 0111 1111 1010 1100 1000 0111 1111 1010 1100 1001 1000 0111 1111 1010 1010 1100 1100 1100 1001 0000 0010 1010 1001 0000 1000 1100 1101 0111 0000 0010 1111 1111 0000 space Direction of “came_from” / /xx \\\\ /\\\ //// Output 1 1 0 \//\ \//\ //// //\/ FIGURE 37 The horizontal axis is time. Authors Fred Ma.4. each box shows a different time. Boxes in the same olumn show the flip-flop contents at a given time. It is important to note the circuit only shows data at one time.

b) At the D-input to each flip-flop. Fill the column (ii) D inputs. 1. FIGURE 40 input rec’d 2nd error 00→01 A 2 #1 #2 #3 #4 Control wires A 4 A 4 A 2 A 2 B 1 C 3 D t=now (t=n+3) 0 B B B 0 12 0 1 2 B 1 C C 3 C 0 D 1 C X D D t=now+1 (t=n+4) t=now D Q 1 1 D 1 (i) (ii) Authors Fred Ma. then you know what the proper decoded output bit is.c) Fill in the data on the D inputs in column (i). and also what was clocked into the column (i) flip-flops (Q). You can guess the states by choosing the lowest H but often you must wait several steps to be sure. #1 #2 #3 #4 FIGURE 39 A input rec’d A B 1 01 A 4 A 2 C D t=now (t=n+2) 02 1 0 13 1 B C B C 1 D t=now+1 D (t=n+3) 0 0 1 1 0 0 1 1 t=now X B X 0 X D C Unknown We haven’t put anything is in these flip-flops at the start X D input to this flip-flop TRELLIS CIRCUIT The clock has advanced one cycle from Figure 38.Convolution Codes input rec’d A B C D t=now decoded bit between t=now and t=now+1 for state A FIGURE 38 01 A 2 o 01 A 2 A 02 1 0 13 1 B C D B C D 0 B 2 1 13C 0 2 If you know the present and next trellis states. show the bit that will be stored on the next clock after t=now. D t=now+1 t=now t=now+1 1 a) Fill in the blanks showing the candidate decoded bits between t=now and now+1 for each state in these two typical trellis steps. 1. Here we inject the data associated with each path into the initial flip flops of the feed-forward shift register. 1999 22 . John Knight January 27.These will be shifted from column (i) along the best four paths. The first row of muxes is shown with dashes because they are redundant. State C has it written in already.

i) How do you find what the data value on that path was between t=n+2 and n+3? Authors Fred Ma. h) Complete filling in the Q outputs. At now which is also t+6. input rec’d 3 A 3 B 2 C 2 D #1 #2 #3 #4 Control wires FIGURE 42 4 A 4 A 11 A A The 1st column of MUXes has been removed. We don’t need them. g) Continue writing in D and Q for the flip-flops. 1. we know the best path ends on B. f) Continue writing in D and Q for the flip-flops.Convolution Codes the up or down position input 10 rec’d 3 A The first column 2 A of muxes is 3 slowly being B 2 B removed from the picture. 2 UP #1 #2 #3 #4 Control wires FIGURE 41 4 #1 A A A 4 #1 A 0 1 0 0 B B B #2 #2 B 1 C 3 C 2 D C 2 D 1t=now+1 (t=n+5) D #4 (t=n+4) t=now (i) (ii) 1. The shaded flip-flops will be removed in the next figure. 4 A 1 3 0 B 03 C 2 A B 0 B B B B 1 C C C C C 0 D t=now (t=n+5) 13 #4 t=now 1 1 D #3 D #3 D 0 C 1 C C 1 (iii) D t=now+1 (t=n+6) 1 D D D D 1. Also write in whether the control wires will switch the muxes to up or down. 1999 23 . John Knight January 27. input rec’d 2 A 3 B 2 C 2 D #1 #2 #3 #4 (i) (ii) Control wires (iii) t=now (iv) FIGURE 43 11 A A 4 A 4 A 4 A 1 2 0 B 04 C 3 A B 0 B B B B 1 C C C C C 0 D t=now (t=n+6) 14 D t=now+1 (t=n+7) t=now 1 D D D D 1.

Then considerif (came_from[A]) AregNxt ={0. //Not storage always @(came_from or memry[A] or memry[B] or memry[C] or memry[D]) begin if (came_from) AmemNxt={1'b0. BmemNxt=memry[C]. memry[C]<=CmemNxt. The following sample code using memory may be useful. Breg. BmemNxt. DmemNxt. reg [1:lat] AmemNxt. CmemNxt=memry[D]. parameter s=2. end end Authors Fred Ma. memry[C]<=0. memry[D]<=0. if (reset) begin memry[A]<=15.Areg}>>1. reg [1:lat] memry [0:t-1]. end always @(posedge clk or posedge reset) begin memry[A]<=AmemNxt.Creg}>>1. Do you take the one on the best path? Do you take the majority of the four? Do you take the first one and assume the others will be the same? Write some pseudocode to implement your strategy to get the dataOut bit. lat=12. Creg. t=s*s. Define a memory array large enough to hold the complete forward trace. 1999 24 . d) The forward trace might be stored in a memory array.memry[A]}>>1. c) Decide a strategy to get the dataOut bit. memry[D]<=DmemNxt. The only advantage of an array is a memory genertor can be used to construct it. John Knight January 27. Then incorporate your previous code into the memory. else AregNxt={0.Convolution Codes b) Develop pseudocode to implement the carry-forward shift registers. B=1. parameter A=0. C=2. DmemNxt=memry[A]. Verilog is very restrictive with arrays. Define a vector for each row to extract bits. A hint as to a possible method follows: Define four registers in the form of: reg [1:latency-1] Areg. CmemNxt. Many CMOS design systems have some sort of memory generator which will be more space and power efficient than flipflops. memry[B]<=0. Dreg. Only large arrays are worth the bother. memry[B]<=BmemNxt. else AmemNxt={1'b0.memry[C]}>>1. //Storage // One can only get at rows of the array directly. D=3.

John Knight January 27. latches must follow the data. Latches cannot be put in the same procedure as flip-flops. Do not use posedge clock. (back) PARTIAL COPY OF FIGURE 17 FIGURE 44 A B 0 A B 1 A 2 A 2 A B 2 3 3 A 2 A 1 10 2 B 11 0 A 3 3 B 2 B B 2 3 B 4 10 1 C D t=n C 1 C 1 C 3 2 C 2 C D t=n+5 1 1 1 1 C 3 C D t=n+7 1 1 1 1 D t=n+1 3 D D t=n+2 t=n+3 x x 1 1 1 1 1 1 D t=n+4 D t=n+6 1 1 1 1 10 1 4 0 1 0 1 t=n+1 1 1 1 1 1 1 1 1 t=n+2 0 0 1 1 t=n+3 t=n+4 t=n+5 t=n+6 1 1 1 0 t=n+7 t=n+8 0 1 0 1 t=n+2 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 t=n+3 t=n+4 t=n+5 t=n+6 t=n+7 t=n+8 FIGURE 45.Convolution Codes 4. When transparent. 1999 25 . You need more than @(clock).6 Some Hints and Answers Solution: to Figure 32. Authors Fred Ma. How not to code a latch (Back) Latches have something happen on both edges. Do not put logic in the same procedure the latch. not with some stray flip-flop. Put the reset for the latch in the procedure for the latch.

Then state a conclusion about how the four blanks would be filled in for an arbitrary trellis step. John Knight January 27. You can guess the states by choosing the lowest H but often you must wait a few steps to decide. 1999 26 . Fill in the blanks showing the decoded bits between t=now and now+1 for each state in these four typical trellis steps.Convolution Codes input rec’d A B C D t=now decoded bit between t=now and t=now+1 for state A FIGURE 46 01 A 2 o 01 A 2 10 A A B 11 A B A B C D 03 13 0 2 02 1 0 13 1 B C D B C D 0 B 2 1 13C 0 2 1 3 0 B 03 C 2 A C C D t=now+1 D t=now+1 t=now t=now+1 12 t=now D 13 D t=now+1 t=now If you know the present and next trellis states. Authors Fred Ma. then you know what the proper decoded bit is.

- 74112
- Convolutional Codes
- BE_E&TC_
- Print
- Teorija Informacija
- sumador diseño digital
- 127786532 Basic Interview Questions on DFT
- Rs Flip Flop
- Digital Electronics (Combinational and Sequential Circuits)
- satellite modulator
- IJERD (www.ijerd.com) International Journal of Engineering Research and Development IJERD
- A0118101111.pdf
- ts_100909v050600p
- 1570215678
- LTE_Basics
- digital mcq
- A6276
- Reporte Contador 9 S
- Ldr
- Hardware Simulator Tutorial.ppt
- Alford C.digital Design VHDL Laboratory Notes.1996
- 2016-2017 Syllab de DIP
- STEP+7+ +Ladder+Logic+for+S7 300+and+S7 400
- ECE480_chap5
- Co Lab Manual II
- Test Your Self General Science
- neon_man
- 74LS259
- ch3
- 74LS164_1_.pdf

- Implementation of Viterbi Decoder on FPGA to Improve Design
- A Pipelined Processing Architecture for Delay Optimized Matching of Data Encoded with Hard Systematic ECC
- FPGA based BCH Decoder
- BER Performance of MIMO with Orthogonal Space Time Block Code Using FEC and Various Modulation Techniques
- Noise Analysis on Indoor Power Line Communication Channel
- Blind Channel Shortening for MIMO-OFDM System Using Zero Padding and Eigen Decomposition Approach
- Segment Combination based Approach for Energy- Aware Multipath Communication in Underwater Sensor Networks
- Federal Election Commission (FEC)
- As NZS 4540-1999 Digital Broadcasting Systems for Television Sound and Data Services - Framing Structure Chan

- VHDL Beginners Book
- Think & Grow Rich
- Finite State Machine
- Copycat Marketing 101 by Burke Hedges
- Test Bench Overview
- Blue Print Success by Shiv Khera 431[1]
- Lecture03 FPGA Doc
- Semiconductor Memories
- Vlsi Design Flow
- Verilog Tutorial
- Lecture03-FPGA
- flip-flop
- Balagurusami Object Oriented Programming cCh1to5
- Einfochip
- SystemVerilogIntroduction
- USA Top 50 Universities
- Chemical Vapor Deposition
- Mosfet Basics
- SOP For VLSI Students
- Epitaxial Growth
- Photo Resists
- Ion Implantation
- Phase Locked Loop
- Kulwant Nagi Latest Resume
- Vlsi Design Flow
- CAT_ Does Reasoning' Puzzle You
- Interview Vlsi
- Vlsi Design Flow
- Domino Logic

Sign up to vote on this title

UsefulNot usefulClose Dialog## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Close Dialog## This title now requires a credit

Use one of your book credits to continue reading from where you left off, or restart the preview.

Loading