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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

A 40 nm Gate Length n-MOSFET

Mizuki Ono, Masanobu Saito, Takashi Yoshitomi, Claudio Fiegna, Tatsuya Ohguro, and Hiroshi Iwai, Senior Member, ZEEE

Abstract- Forty nm gate length n-MOSFETs with ultrashallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hotcarrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as v d falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 nm region if v d is less than or equal to 1.5 V.

lQ70

l=Year

1990

2000

Fig. 1. Trends in the fabrication of small geometry MOSFETs.

TABLE I NEW DESIGNING METHOD

Conventional 0.1 pm n-MOSFETs

I. INTRODUCTION OSFET down-sizing has been continued for the past 25 years, and even higher integration density and greater speed has been achieved in LSIs. Fig. 1 shows the reduction in MOSFET gate length with time at the research level. In 1974, R. H. Dennard et al., announced a 1.0 pm gate length nMOSFET operating at room temperature [ 11. After 13 years of work, in 1987, G . A. Sai-Halasz et al., published a paper on 0.1 pm gate length n-MOSFETs operating at room temperature. At the same time, they also fabricated a 70 nm gate length nMOSFET which operates at liquid nitrogen temperature [2]. In 1992, five years later, T. Hashimoto et al., presented a 70 nm gate length n-MOSFET for room-temperature operation [3]. However, this tendency for gate lengths to fall now seems to have stagnated, as shown in the figure. Extrapolation of a fitted line would imply that sub-50 nm gate length n-MOSFETs should have appeared. In fact, there have been intensive studies of the fabrication of MOSFETs with gate lengths in the 0.1 pm range [ 13-[ 113, but it is proving very difficult to go to sub-50 nm gates and make MOSFETs that operate. There are several reasons for this, and we discuss them here. MOSFET miniaturization has followed the guidelines laid out in the scaling method originally proposed by R. H. Dennard et al. [l]. According to their scaling theory, gate
Manuscript received March 14, 1995; revised May 30, 1995. The review of this paper was arranged by Associate Editor D. P. Verret. M. Ono, M. Saito, T. Yoshitomi, and T. Ohguro are with the Research and Development Center, Toshiba Corporation, Kawasaki 210, Japan. C. Fiegna is with the University of Ferrara, Ferrara, Italy. IEEE Log Number 9413954.

40-nm gate length n-MOSFETs

Lg

loom

3
x Yl

m] nl m

1 1% 0 i 3

oxide thickness has to be reduced and substrate impurity concentration has to be increased as gates are reduced in size. However, gate oxide thickness have already reached 3 4 nm-the tunneling leakage current limit for the gate insulator-and substrate impurity concentrations have reached 5 x 1017-1 x cmp3-the tunneling leakage current limit for the source/drain to substrate p-n junctions. Thus, it can be said that this scaling method has reached its limit since the parameters can be scaled no further. In this work, we modify the scaling method, as shown in Table I, and succeed in the fabrication of 40 nm gate length n-MOSFETs. According to our new designing method, when reducing the gate length (L,) from 100 nm to 40 nm, the gate oxide thickness (toz),substrate impurity concentration (Nsub), and supply voltage are maintained at the values used in 100 nm gate length MOSFETs. Instead, the junction depth of source and drain is reduced by 3/4-from 40 nm to 10 nm. In order to realize ultra-thin poly silicon gate electrodes of 40 nm and ultra-shallow source and drain junctions of 10 nm, special techniques have been developed.

0018-9383/95$04.00 0 1995 IEEE

ONO et al.: 40 NM GATE LENGTH n-MOSFET

1823

Lg 40 nm

8
PSG sidewalls / 1 y (3 x 1O2bm9) " F

(a)

L, 1O n Om

II

polysilicon deposition gate lithography (excimer)

resist thinning (02 plasma ashing)

polysilicon RiE

L d 37 nm
(b)

XI 45nm
As ion implantation (30 keV 5 x 101%m'2)

PSG etching back

Fig. 2. Schematic cross sections of n-MOSFET's. (a) Schematic cross section of a 40 nm gate length n-MOSFET. (b) Schematic cross section of a conventional arsenic ion implanted 100 nm gate length n-MOSFET.

As ion implantation

Fig. 4(a) explains the gate electrode formation process. First, in situ phosphorous-doped poly silicon is deposited to 200 nm thickness on the 3 nm gate oxide. Then, gate lithography with an excimer stepper is carried out and the 200 nm resist Fig. 3. Fabrication process for 40 nm gate length n-MOSFET's. pattern is developed. A special technique is then used-resist thinning by isotropic oxygen plasma ashing [12]. The resist pattern is reduced to 40 nm in length. Reactive ion etching 1 . SAMPLE 1 FABRICATION of the polysilicon is then carried out using the thinned resist Fig. 2(a) shows a schematic cross section through a 40 nm as a mask, and the result is 40 nm-length polysilicon gate gate length n-MOSFET in comparison with a conventional electrodes. The shape of gate electrodes obtained this way is 100 nm MOSFET in Fig. 2(b). The gate oxide thickness shown in Fig. 5. is 3 nm and the source and drain near the channel region The ultra-shallow 10 nm sources and drains were achieved have junction depths of around 10 nm. Instead of the SiN for the first time by using the technique of solid phase diffusion sidewalls of a conventional MOSFET, PSG (phospho-silicate (SPD) from the PSG sidewalls as shown in Fig. 4(b). First, glass) sidewalls are adopted. a 150 nm-thick PSG film with a phosphorus concentration Fig. 3 shows the process steps for the fabrication of these of 3 x loz1 cm-3 is deposited by APCVD (Atmospheric 40 nm n-MOSFET's. After the conventional LOCOS isolation Pressure Chemical Vapor Deposition). The oxide layer of a process, the channel region is doped by boron ion implantation. few nanometers resulting from the precleaning treatment is A 3 nm gate oxide layer is then grown by 800C thermal not removed before deposition, so as to suppress phosphorus oxidation for 8 min. For the formation of 40 nm gate electrodes deeper diffusion into the substrate. PSG gate sidewalls 190 nm and 10 nm-deep source and drain junctions, special techniques in width are formed by the conventional sidewall fabrication have been developed. They are, respectively, resist thinning by process. Then, arsenic is implanted outside of these sidewalls oxygen plasma ashing and phosphorus solid phase diffusion with an energy of 30 keV to a dose of 5 x 1015 cmP2 in from PSG sidewalls. order to create the deeper source and drain regions. Following
i

Isolation (LOCOS) Channel doping 0 ion implantation (B, 30 keV, 3.6 x 10'3cm'2) furnace annealing (1,O0OoC, 120 min.) Gate oxidation (800C, 8 min.) Gate electrode formation in-situ phosphorous-doped poly silicon deposition gate lithography (excimer) resist thinning gate RiE Sourddrain formation PSG deposition (150 nm) etch back RIE ion implantation (As, 30 keV, 5 x 10'5cm-2) rapid thermal annealing (l,OOOC, 5 or 10 sec.) Metallization

(l,OOo"C, 5sec 1,OOo"C, 10 sec)

(b) Fig. 4. Schematic cross sections at each major process step. (a) Schematic cross sections at major process steps in the gate electrode fabrication process. (b) Schematic cross sections at major process steps in the source and drain fabrication process.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

E 0

50

depth [nm]
Fig. 6 . SIMS profiles of solid phase diffused phosphorous from PSG films, boron from BSG films, and conventionally implanted arsenic.

(b)

(C)

Fig. 5. High-resolution SEM photographs of 40 nm gate length n-MOSFETs: (a) after gate poly-silicon RIE, (b) top view, and ( c ) magnified view of (b).

E c

this, RTA (rapid thermal annealing) is carried out at 1000C for 5 or 10 s. During the RTA, phosphorus is solid-phasediffused from the PSG sidewalls into the substrate to form an ultra-shallow diffused layer of around 10 nm thickness near the channel region. At the same time, implanted arsenic in the deeper region is activated. Fig. 5(b) and (c) shows top views of a gate electrode and the PSG sidewalls. Fig. 6 shows the profile of phosphorus diffused by solid phase diffusion from the PSG sidewalls as measured by SIMS (Secondary Ion Mass Spectroscopy). In this figure, the profiles of boron diffused from BSG (boron doped silicated glass) and implanted arsenic after activation are also shown. In the case of conventionally ion-implanted arsenic, the junction depth is around 40 nm. It is difficult to further reduce this figure, because of impurity tailing effects during ion implantation and enhanced diffusion of the arsenic during heat treatment for activation caused by ion implantation damage. Quite shallow junction formation of 20 nm is reported in [ 111. The method used in that report needs some other special technique such as low energy ion implantation. In the case of solid phase diffused phosphorus, it is easy to obtain 10 nm junctions with high doping concentration. In the case of boron, which is diffused from the BSG film, the minimum junction depth must be around 30 nm in order to achieve sufficiently high impurity concentration at the surface, since borons segregation coefficient is small and boron concentration at the silicon interface tends to become lower. On the other hand, when phosphorus is diffused from the PSG film, the segregation coefficient is larger, and so an ultra-shallow junction with a high surface impurity concentration can be obtained. The dependence of junction depth and sheet resistance on RTA conditions is shown in Fig. 7(a) and (b), respectively. RTA at

1
60 20

BSG 900C 950C

O O 5 10 15 20 25 annealing time [sec]

(a)

BSG

annealing time [sec]

(b)

Fig. 7. Dependence of junction depth and sheet resistance on rapid thermal annealing conditions. (a) Dependence of junction depth on rapid thermal annealing conditions. (b) Dependence of sheet resistance on rapid thermal annealing conditions.

1000C for 5 s and 10 s was found to give relatively low sheet resistance (less than 10 kR/O) for 10 nm junctions. 111. EXPERIMENTAL RESULTS Fig. 8(a) and (b) shows the Id-Vg and I d - V d characteristics of a 40 nm gate length n-MOSFET at room temperature. The RTA conditions in this case were l00OoC for 10 s.

ONO et al.: 40 NM GATE LENGTH n-MOSFET

1825

TABLE II PROCESS PARAMETERS 40 nm GATELENGTH FOR n-MOSFETs

RTA cond. 1,Ooo0c,5 sec 1,Ooo0c,10 sec

4onm

26nm
l0nm
I

23nm

3 nm

12nm
I

10 -14 -1.0

I
I

bJd

190 nm 10 pm

0.0

1.o

2.0

W E

I
I

TABLE 111 DEVICE PARAMETERS 40 nm GATELENGTH FOR n-MOSFETs

t 6.0 7-0 5.0 4 E 4.0

- 3.0
U

2.0
1.o

I
I 0.4

Id

I470mNmm

~ 1 m ~ m m

V
DEPENDENCES L , OF
f f

-8.0
Fig. 8. (a) Idd-\\
1d-t;

0.5

1.0

1.5
(b)

2.0

ON

TABLE IV RAPID THERMAL ANNEALING CONDITIONS

Vd [VI

La RTA cond. 1,Ooo0c, 5sec 1,000c,20sec l,osooc, 10 sec As I/I I I

X J

and I d - v d characteristics of a 40 nm gate length n-MOSFET: characteristics and (b) I d - v d characteristics.

1onm 22nm 51 nm

L,= 25 nm 9nm 0 nm 0 nm

I Lg=loonm
I
85nm

The 40 nm gate length n-MOSFETs operate quite normally at room temperature even at V = 2 V. The process and d device parameters for 40 nm gate length n-MOSFETs at V = 1.5 V are shown in Tables I1 and 111, respectively. At d Vd = 1.5 V, the S-factor is 96.5 mV/dec and the threshold voltage extrapolated from the Id-V, curve is 0.42 V. The maximum value of transconductance (gm) is 428 mS/mm while Id at Vg-Vth = 1.5 V is 581 mA/mm. Conventional 40 nm gate length n-MOSFETs with arsenic ion-implanted sources and drains do not operate at all, even at V = 50 d mV, due to punch-through. Here it should be noted that the effective channel length, L , f f , of n-MOSFETs fabricated using the SPD technique is longer than that of conventional n-MOSFETs with the same gate length, since the junction depth of diffusion layers formed by the SPD technique is much less than that of conventional diffusion layers. The effective channel length of 40 nm gate length n-MOSFETs fabricated by the SPD technique is roughly the same as that of 80 nm gate length devices with conventionally fabricated sources and drains. Table IV shows the dependence of junction depth and effective channel length on rapid thermal annealing conditions. This table makes it clear that 40 nm gate length n-MOSFETs cannot be fabricated using the conventional ion implantation technique. The drain breakdown characteristics of a 40 nm gate length n-MOSFET are shown in Fig. 9(a) and compared with those of

45nm

69 nm 29 nm 37 .~ nm

a 100 nm gate length n-MOSFET with a conventional arsenic ion implanted source and drain in Fig. 9(b). Characteristics for a long channel n-MOSFET with source and drain fabricated by the SPD technique are shown in Fig. 9(c). The breakdown voltage of a 40 nm gate length n-MOSFET at V, = 2 V is as high as 3.5 V, though significant drain current reduction is observed after breakdown due to hot carrier injection. This breakdown voltage is almost equivalent to that of 100 nm gate length n-MOSFETs with conventional sources and drains, and to that of long channel ( L , = 1.0 pm) n-MOSFETs with sources and drains formed by SPD. The short channel effects on AVfh and S-factor at v = 1.5 d V are shown in Fig. 10(a) and (b), respectively. In the case of n-MOSFETs made by the SPD technique, and particularly when the annealing conditions are l000OC for 10 s, AVfh is 0.16 V even for the case of L, = 40 nm. In contrast, conventional samples do not operate when L, = 40 nm. The S-factor of SPD n-MOSFETs is around 95 mV/dec even for 40 nm gate length devices while in the case of long gate length devices it is slightly larger than 80 mV/dec. The threshold voltage scatter of the n-MOSFETs were also investigated. Fig. 1l(a) shows the distribution of threshold voltage values extrapolated from the Id-V, curves at V = d

1826

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

6.0 n5.0 a 4.0 E U 9 3.0 2.0

1.o

v, = 0.2 to 2 v (0.2 v step)

n

Om* c

m
I
4

0.0 -

8
1.0

5 -0.2

'-8.0
8.0 7.0 6.0 a 5.0 E 4.0 U 2 3.0 2.0 1.o

2.0
vd

3.0

4.0

[VI

8
8
0

95 90 85 80

>E
IC,

f
0

'-8.0

1.0

2.0

3.0

4.0

Mi [VI
(b)

6.0 5.0 E 4.0 U

v, = 0.2 to 2 v (0.2 v step)

75 0.01
(b)

0.1
Lg

Wml

s 30 .

and S-factor on L,: (a) Dependences of Fig. 10. Dependences of A\ih on L , and (b) dependences of S-factor on L,.

(C) Fig. 9. Drain breakdown characteristics. (a) Drain breakdown characteristics of a 40 nm gate length n-MOSFET. (b) Drain breakdown characteristics of a 100 nm gate length n-MOSFET with conventionally fabricated source and drain. (c) Drain breakdown characteristics of a 1.O p m gate length n-MOSFET with source and drain fabricated using solid phase diffusion.

2 V. In the case of solid phase diffused devices, the standard deviation ( a ) of Vth for 40 nm gate length n-MOSFET's is 0.052 V and that for 100 nm gate length devices is less than 0.01 V. This is about one-third of that in the case of conventional devices with 100 nm gate length. In devices fabricated by the SPD technique, short channel effects are almost totally suppressed at gate lengths above 100 nm, so variations in gate length do not affect the threshold voltage at all. If we assume the threshold voltage scatter to fit a Gaussian distribution, the probability of [I& - Kh.meanI > 6avth is

1/10' and the probability of l K h - V t h . m e a n ) > 7avth is 1/10l2, where is the mean value of Kh. In other words, if the SPD technique is used to fabricate 100 nm gate length n-MOSFET's, the threshold voltages of 1G transistors would be within 0.06 V (6 a ~ ~and h )transistors would be ~ 1T within 0.07 V (7 avth>. The data and estimates given above are for n-MOSFET's with a gate width (W,) of 10 pm. In the case of logic and analog LSI's, transistors with larger gate widths are often used. In the memory LSI's, however, narrow gate transistors are typical. We now turn our attention to the dependence of threshold voltage variation on gate width. Assuming a Gaussian distribution, the dependence of the threshold variation on gate width can be expressed as
a v t h ( ~ ,= const. w,-''~ )

Fig. ll(b) shows the dependence of standard deviation of threshold voltage on device width. Even at W , = 100 nm, the uvth value of 100 nm gate length MOSFET's is around 80 mV. It is known that fluctuating impurity levels in the substrate have an effect on the variation in threshold voltage [ 131.

ONO et al.: 40 NM GATE LENGTH n-MOSFET

1827

0.

S Y F
LI " .
+

IPSG 1,OoOoc, 10 sec]

IAs Ion lmplantatlonl

d 200

100:

' '

"""

.....

9
b

.........

..

.............

..

1 0.2

'

"""'

.
2
OVth

.............

... .., ...

'-

Total devlatlon Devlationdue to lmpurlty fluctuations

0.5 1

5 10 20
KI 4 . 5 V
(b)

Fig. 11. Distribution of V t h : (a) distribution of Vtt8 for solid phase diffused n-MOSFET's with various gate lengths and conventional LDD n-MOSFET's, and (b) dependence of standard deviation of Vth on gate width.

This component of is expressed as

due to impurity level,

.........................
oVth(Na),

In terms of L, and W,, this can be written as follows:

a v t h ( N a ) = - L, W,S N , - 1'2 QbToz (
2Eoz

(2)
KI-1.5V

where S is the thickness of the depletion layer. The dependence of F V t h ( N a ) on W, and L, when To, = 3 nm, Na = 1x 10l8 cmP3 is also plotted in Fig. ll(b). It is worthy of note that the impurity fluctuation component is about one order of magnitude smaller than the total threshold voltage variation. Fig. 12(a) and (b) shows, respectively, the dependence of drain current ( I d ) at v d = V,-&h = 1.5 V and the maximum value of transconductance ( g m ) at v d = 1.5 V on gate length. Because of velocity saturation effects in short channel devices, and the relatively higher sheet resistance of sources and drains even when fabricated by the SPD technique, I d and gm tend to saturate as L, falls below 200 nm. Despite this, an increase of around 30% is observed as L, is reduced from 100 nm to 40 nm. In the case of conventional arsenic ion implanted devices, the significant short channel effects mean that I d and, more particularly, gm values do not tend to saturate down to L, = 100 nm. The intrinsic gm value, gm,int, is estimated using the equation g m , i n t = g m / ( l - R s o u r c e g m ) , where R s o u r c e is the source resistance of the transistor. It is difficult to extract

0.01
(c)

0.1

Lg b m l
Fig. 12. Dependences of drain current and transconductance on gate length. (a) Dependence of drain current on gate length. (b) Dependence of transconductance on gate length. (c) Dependence of the upper bound of transconductance on gate length.

precise RSOurCe values for ultra-small transistors so, in this case, RSouTCe estimated as half the total drain-to-source is resistance of transistors with the smallest gate length ( L , = 40 nm for the SPD transistors and L, = 100 nm for the conventional arsenic ion implanted transistors). The gate bias is the gm,max condition for v d = 1.5 V and the drain bias is set to 50 mV. RSourCe values obtained in this manner are given in the Fig. 12(c). They are greater than the RSoUrCe values which would be expected in reality, so the true g m , i n t should be less than the calculated value. The calculated g m , i n t is plotted in Fig. 12(c). Velocity overshoot was not observed in 40 nm gate

1828

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

10 -

0 l,oOooc, 50 l o o C l 8ec ,0',O

e n

lo9;

10";

00 .1

01 . Lg " I

Fig. 14. Dependence of impact ionization rate on gate length.

1" 0
Y

r
0 " . 0 0

ooo
0
O0 0

10

a
9

loe
10 4

F r
Y

-b=

40nm _ - - b=100 nm _ _ _ _ _ b=170 nm

v lo-'

1-O 0'

v n

9 4 lo4: >

+
a
QD

-lod
Fig. 13. Dependences of impact ionization rate and substrate current on drain voltage. (a) Dependence of impact ionization rate on drain voltage. (b) Dependence of substrate current on drain voltage.

PSG 1,OOOC, 10 sec

0.5

0.6
I / ( v d -vsat)

0.7

a
on l / ( \ > -

[IN]

Fig. 15. Dependence of l o g ( ( I s , , b / I d ) / ( \ >

-\bat))

length n-MOSFET's. This result does not necessarily deny the possibility of velocity overshoot, but the evidence of velocity overshoot could not be observed in the case of our experiment. We also investigated hot carrier related phenomena in 40 nm gate length n-MOSFET's. Fig. 13(a) and (b) shows the dependence of impact ionization rates, I s u b / I d , and substrate current, Is&, on drain voltage, respectively. Both impact ionization rate and I&, fall significantly as v d goes below 1.5 V. Fig. 14 shows the dependence of impact ionization rate on gate length; there is only weak dependence. Furthermore, impact ionization rate has only weak dependence on the conditions of source and drain formation. More detailed analysis of impact ionization rate has also been carried out. In the analytical model, the impact ionization rate is proportional to (Vd - V,,,) exp (-A/(Vd - V,,t)) [141. Here, Vsat is the potential at the point where the electron velocity saturates and A is some constant. The values of log ((r,,b/rd)/(vd-v,,,)) are plotted versus 1 / ( V d - V,,,) in Fig. 15. The log((Isub/Id)/(Vd - V s a t ) values increase ) slightly with falling gate length. The dependence of im-

10" [
Miruno, e. al. [15] t

3 *loa OD

t
experiment

01 . L g kml
Fig. 16. Dependence of

1
= 0.6

v-' .

Isub/Ici

on gate length for 1/(Vd -

pact ionization rate-&,b/ld value at l / ( V d - V,,,) = 0.6 V - l - o n L, is plotted in Fig. 16. G. G. Shahide et al., reported

ONO er al.: 40 NM GATE LENGTH n-MOSFET

1829

TI00

L
II

s cv
>
T
E
II
0

the dependence of Is&, on v d (Fig. 13(b)), it can be estimated that I d degradation over 10 years (even with a duty ratio of 100%) would be less than 10% for V d = 1.5 V. Thus, hot carrier degradation will not be a problem with the 40 nm generation of n-MOSFETs.

10

IV. CONCLUSION
The first 40 nm gate length n-MOSFETs have been realized by adopting 10 nm source and drain junctions. These shallow source and drain junctions were achieved by solid phase diffusion from PSG sidewalls. It has been confirmed that 40 nm gate length n-MOSFETs fabricated in this way operate quite normally at room temperature. It has also been confirmed that this solid phase diffusion technique for the fabrication of source and drain layers is very effective for the suppression of short channel effects. We have shown that both substrate current and impact ionization rate decrease significantly as the drain voltage is reduced below 1.5 V and that the dependence of impact ionization rate on gate length is very weak. If the devices are operated at a v d of 1.5 V or below, the drain current degradation after 10 years is estimated to be less than 10%. Thus, hot carrier degradation will not be a problem in the 40 nm region. ACKNOWLEDGMENT The authors thank K. Fujisaki, T. Matsushita, and T. Ohtomo for their support in sample fabrication.

ua

vd=

2.2 v

1
10

100

1000

stress time [sec]

REFERENCES

lsub @A]
(b)

10

100

Fig. 17. Dependence of degradation rate of I d on stress time and Isub. (a) Dependence of degradation rate of I d on stress time as a function of \;i during stress tests. (b) Dependence of degradation rate of I d on I S u b during the stress tests.

that the impact ionization rate decreases as the gate length is reduced in the 0.1 pm region and that the reason for this is that the electron temperature cannot reach its maximum steadystate value in very short channel devices because of the finite energy relaxation time [15]. On the other hand, T. Mizuno et al., reported that the impact ionization rate increases as gate lengths fall in the 0.1 pm region because of enhanced carrier energy resulting from the strong channel electric field [16]. In our case, the impact ionization rate increases very slightly with falling gate length. This agrees with the results reported in [17]. Hot carrier stress tests were carried out for the 40 nm gate length n-MOSFETs. Fig. 17(a) shows the dependence of drain current degradation rate on stress time, where the devices were stressed under conditions of maximum substrate current. The rate of drain current degradation after 1000 s of stress is shown in Fig. 17(b). From the dependence of AIdlId on stress time given by Fig. 17(a), and on I& (Fig. 17(b)), and

[I] R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFETs with very small physical dimensions, IEEE J . Solid-State Circuits, vol. SC-9, no. 5, pp. 256-268, 1974. [2] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid, M. R. Polcari, H. Y. Ng, P. J. Restle, T. H. P. Chang, and R. H. Dennard, Design and experimental technology for 0.1-pm gate length low-temperature operation FETs, IEEE Electron Device Lett., vol. EDL-8, pp. 463466, 1987. [31 T. Hashimoto, Y. Sudoh, H. Kurino, A. Narai, S. Yokoyama, Y. Horiike, and M. Koyanagi, 3 V operation of 70 nm gate length MOSFET with new double punchthrough stopper structure, in Ext. Abs. Int. Con$ Solid State Devices Materials, Aug. 1992, pp. 490492. 141 T. Y. Chan and H. Gaw, Performance and hot-carrier reliability of deepsubmicrometer CMOS, in IEDM Tech. Dig., Dec. 1989, pp. 71-74. [5] G. G. Shahidi, D. A. Antoniadis, and H. 1. Smith, Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel length, in IEDM Tech. Dig., Dec. 1986, pp. 82&825. [6] M. Aoki, T. Ishii, T. Yoshimura, Y. Kiyota, S. Iijima, T. Yamanaka, T. Kure, K. Ohyu, T. Nishida, S. Okazaki, K. Seki, and K. Shimohigashi, 0.1 p m CMOS devices using low-impurity-channel transistors (LICT), in IEDM Tech Dig., Dec. 1990, pp. 939-941. [7] J. P. Mieville, J. Barrier, Z. Shi, and M. Dutoit, Mix and match lithography for 0. I p m MOSFET fabrication, Microelectron. Eng. 13, pp. 189-192, 1991. [81 R. H. Yan, K. F. Lee, D. Y. Jeon, Y. 0. Kim, B. G. Park, M. R. Pinto, C. S. Rafferty, D. M. Tennant, E. H. Westerwick, G. M. Chin, M. D. Moms, K. Early, P. Mulgrew, W. M. Mansfield, R. K. Watts, A. M. Voshenkov, J. Bokor, R. G. Swatz, and A. Ourmazd, High-performance 0.1-pm room temperature Si MOSFETs, in Symp. VLSI Tech. Dig., June 1992, pp. 8 6 8 7 . [91 A. Tonumi, T. Mizuno, M. Iwase, M. Takahashi, H. Niiyama, M. . Fukumoto, S. Inaha 1 Mori, and M. Yoshimi, High speed 0.1 p m CMOS devices operating at room temperature, in Ext. Abs. Inr. Con$ Solid State Devices Materials, Aug. 1992, pp. 487489.

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[IO] M. Saito, T. Yoshitomi, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, H. S. Momose, Y. Katsumata, Y. Ushiku, and H. Iwai, An SPDD PMOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics, in ZEDM Tech Dig., Dec. 1992. [ I l l A. Hori, H. Nakaoka, H. Umimoto, K. Yamashita, M. Takase, N. Shimizu, B. Mizuno, and S. Odanaka, A O.05pm-CMOS with ultra shallow source/drain iunctions fabricated bv 5 KeV ion imulantation and . rapid thermal annealing, in IEDM Tech dig., Dec. 1 9 9 4 : ~ ~485-488. [I21 J. Chung, M.-C. Jeng, J. E. Moon, A. T. WU, T. y . Chan, p. K, KO, and C. Hu, Deep-submicrometer MOS device fabrication using a photoresist-ashing technique, IEEE Electron Device Lett., vol. 9, pp. 186-188, 1988. [I31 T. Mizuno, J. Okamura, and A. Toriumi, Experimental study of threshold voltage fluctuations using an 8k MOSFETs array, in Symp. . . VLSI Tech. Dig., May 1993, pp. 4 1 4 2 . and c Hu, A simple method to characterize [I4] T y Chan K substrate current in MOSFETs, IEEE Electron Device Lett., vol. EDL5. DD. 505-507, 1984. [151 G. 6. Shahidi, D. A. Antoniadis, and H. I. Smith, Reduction of channel hot-electron-generated substrate current in sub-I 50-nm channel length Si MOSFETs, IEEE Electron Device Lett., vol. 9, pp. 497499, 1988. [16] T. Mizuno, A. Toriumi, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, and M. Yoshimi, Hot-carrier effects in 0.1 p m gate length CMOS devices, in IEDM Tech Dig., Dec. 1992, pp. 695498. [I71 H. Kurata, Y. Nara, and T. Sugii, Universality of impact ionization rate in 0.1 p m Si MOSFET, in Ext. Abs. In?. Con$ Solid Stare Devices Materials, Aug. 1994, pp. 883-885.

Masanobu Saito, for a photograph and biography, see p. 1520 of the August 1995 issue of this TRANSACTIONS.

Takashi Yoshitomi, for a photograph and biography, see p. 1520 of the August 1995 issue Of this

Claudio Fiegna, for a photograph and biography, see p. 1520 of the August 1995 issue of this

Tatsuya Ohguro, for a photograph and biography, see p. 922 of the May 1995 issue of this

Mizuki Ono, for a photograph and biography, see p. 922 of the May 1995 issue of this TRANSACTIONS.

Hiroshi Iwai (SM93) , for a photograph and biography, see p. 375 of the March 1995 issue of this TRANSACTIONS.