Bulacan State University

COLLEGE OF ENGINEERING
ELECTRONICS ENGINEERING DEPARTMENT

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS IN

ECE 406 – CORRELATION

WRITTEN REPORT:
MICROPROCESSOR 1 AND 2

SUBMITTED BY:
ABUEL, Angelo James

ARCEO, Zharmaine L.

JUMAQUIO, Abbey C.

MADLANGSAKAY, Neiyah

SATAIRAPAN, Jhazmin Kyle G.

ECE – 4C
JUMAQUIO, Abbey C.

Algorithmic State Machine

 "ASM" is "Algorithmic State Machine" which is same as "Synchronous Sequential

Circuit"

 The ASM Chart is an Alternative way for describing "FSM" and is similar to
"Conventional Flow Chart."

 A Conventional Flow Chart describes the sequence of "Procedural Steps" and

"Decision Paths" for an Algorithm without any concern for their "Timing
Relationship".

 The ASM Chart on the other hand describes the "Sequence of Events" as well as
the "Timing Relationship" between the states of a sequence controller and the
events that occur while going from one state to the next state after each clock
edge.

There are three basic elements in an ASM chart.

1. State Box - A state box is represented by a rectangle. It has an input (e.g., x) and
an output. The state of the system is usually denoted by a capital letter, such as
S.

2. Decision Box - A decision box is represented by a diamond shape. It receives an

input and produces two possible outputs, typically labeled 0 or 1.

3. Conditional Box - A conditional box is represented by an oval shape. It takes an

input from the decision box and produces an output (for example, z). That means
this input will always come from the decision box, and it will go towards the state
box
1. Draw the ASM Chart

(Source: ASM chart || Algorithmic State Machine || How to draw ASM chart || ASM charts
|| ASM chart Examples)

a. Start from 𝑆0 x

S0

b. Now it will go to the decision box. The decision will be taken depending on the input x.
x

S0

0 x 1
c. For 0/0, both input and output are 0. When the input is 0, it will remain in the same state
and go to 𝑆0 . x

S0

0 x 1

d. From 𝑆0 , when the input is 1, the output is also 1, and it goes to 𝑆1 . Since the output is 1,
a conditional box is needed. Here we have the output denoted by z.
x

S0

0 x 1

S1
e. Now from 𝑆1 , it will go to the decision box.

S1

0 x 1

f. When the input is 1, it remains in the same state.

S1

0 x 1

g. When the input is 0, it goes to state S2, and it has an output of 1. That means we have to
add a conditional box here. Here we’ll have the output z, and it will go to S2.

0 x

z
h. Draw the state box S2. Then apply the same concepts and rules earlier. This will be the full
ASM Chart. x

S0

0 x 1

S1

0 x 1

S2
z

0 x 1
 2. Convert the Mealy State Diagram to ASM Chart (Source: Unit 5 || ASM Chart || #TMSY ||
CSE)

a. States: S0, S1, S2. These will become the State Boxes in the ASM chart.
b. Input Variable: x Output Variable: z
c. After each State Box, draw Decision Boxes for the input variable x to determine
the next state.
d. State S0
- If x = 0, the transition is 0/0 back to S0.
- If x = 1, the transition 1/0 is S0 to S1. The output z is 0. The next state is S1.
Since the output is 0, you do not need a Conditional Output Box, as outputs
that are 0 by default are often omitted for simplicity.
e. State S1
- If x = 0: The transition is 0/0 to S2.
- If x = 1: The transition is 1/0 back to S1. The output z is 0. The next state is S1.
f. State S2
- If x = 0: The transition is 0/0 back to S0.
- If x = 1: The transition is 1/1 to S1. The output z is 1. The next state is S1.
- Draw a Conditional Output Box with the output z set to 1.
Answer:
3. Convert the Mealy State Diagram to ASM Chart (Source: Unit 5 || ASM Chart || #TMSY ||
CSE)

Output = 1

a. States: S0, S1, S2, S3, S4, S5. The code inside the State Box is the binary encoding for
the state (e.g., S0 is '000', S1 is '001', etc.)
b. Transitions from S0 ('000')
- x = 0, the path loops back to S0 ('000').
- x = 1, the path moves to the next state, S1 ('001').
- Both outputs are z = 0, so there is no Conditional Output Box.
c. Transitions from S1, S2, S3, S4 ('001', '010', '011', '100')
- These states follow the exact same pattern as S0
- x = 0, the path loops back to the current state. No Conditional Output Box (z =
0)
- x = 1, the path moves to the next sequential state Si+1. No Conditional Output
Box.
d. Transitions from S5 ('101'):
- x = 0, the path loops back to S5 ('101'). No Conditional Output Box (z = 0).
- x = 1, the path moves to a Conditional Output Box labeled z, which implies z =
1. The path then loops all the way back to the starting state, S0 ('000').
Answer:
4. Convert the Moore State Diagram to ASM Chart (Source: Unit 5 || ASM Chart || #TMSY ||
CSE)

a. States: S0, S1, S2, S3. These will become the State Boxes in the ASM chart.
b. Outputs: In a Moore machine, the output is associated with the state itself. The
state diagram shows the state and output as State/Output (e.g., S0/0).
c. After each State Box, draw Decision Boxes for the input variable x to determine
the next state.
d. Transitions from S0.
- If x = 0 (the '0' path), the flow loops back to the beginning of S0.
- If x = 1 (the '1' path), the flow moves to the S1 State Box.
e. Transitions from S1.
- If x = 0 (the '0' path), the flow moves to the S2 State Box.
- If x = 1 (the '1' path), the flow loops back to the beginning of S1.
f. Transitions from S2.
- If x = 0 (the '0' path), the flow moves back to the beginning of S0.
- If x = 1 (the '1' path), the flow moves to the S3 State Box.
g. Transitions from S3.
- If x = 0 (the '0' path), the flow moves to the S2 State Box.
- If x = 1 (the '1' path), the flow moves to the S1 State Box.
h. Note: A Moore state diagram does not use a conditional box because its outputs
are determined solely by its current state, not by any conditional input logic. It is
only used for Mealy.
Answer:
Objective Type (Source: https://www.scribd.com/document/561532251/MCQ-UNIT-4)

1. In an ASM chart, Mealy type of outputs

a) Cannot be represented

b) Can be represented by conditional output boxes

c) Can be represented by writing output state variables inside state box

d) Can be represented inside the decision boxes

2. Moore type of outputs are

a) Independent of the inputs

b) Dependent only on the inputs

c) Dependent on present state and inputs

d) Dependent on type of hardware used for implementation

3. An algorithmic state machine is the same as

a) Synchronous sequential circuit

b) Clocked sequential circuit

c) Finite state machine

d) All of the above

4. A decision box in an ASM chart

a) Does not have exit paths

b) Has only one exit path

c) Has two exit paths

d) Has one entry and one exit path

Satairapan, Jhazmin Kyle G.

ASYNCHRONOUS SEQUENTIAL UNIT

1. In an asynchronous sequential circuit, state changes are triggered by:

A. Clock pulses
B. Input changes (events)
C. A fixed periodic signal
D. A stored memory cell
Answer: B

Source: https://www.nprcolleges.org/site/download?file=CS8351-+DPSD+Unit+IV.pdf

2. What is the major difference between synchronous and asynchronous sequential

circuits?
A. Asynchronous circuits always faster
B. Asynchronous circuits don’t require a clock
C. Synchronous circuits never suffer race condition
D. There is no difference
Answer: B

Source: https://www.studocu.com/row/quiz/chapter-9-asynchronous-sequential-logic/6297445

3. The effect of change in input causing more than one state transition is called:
A. Undefined condition
B. Race condition
C. Reset condition
D. Ideal condition
Answer: B

Source: https://compsciedu.com/mcq-questions/Digital-Logic-Design/Asynchronous-Sequential-
Logic/

4. During the design of asynchronous sequential circuits, it is more convenient to name the
states by letter symbols than binary values. What do you call to this table?
A. Transition table
B. State Table
C. Flow Table
D. Implication Table

Answer: C

Source: https://www.nprcolleges.org/site/download?file=CS8351-+DPSD+Unit+IV.pdf
 5. What is the correct description of this asynchronous sequential circuit?

AND
OR
OR AND

A. 𝑦 = 𝑥1 𝑥2 + (𝑥1 + 𝑥2 )𝑦 ; 𝑧 = 𝑦
B. 𝑦 = 𝑥1 + 𝑥2 + (𝑥1 + 𝑥2 )𝑦 ; 𝑧 = 𝑦
C. 𝑦 = 𝑥1 𝑥2 + (𝑥1 𝑥2 ) + 𝑦 ; 𝑧 = 𝑦
D. 𝑦 = (𝑥1 )𝑥2 + (𝑥1 /𝑥2 )𝑦 ; 𝑧 = 𝑦

Answer: A

SOLUTION:

AND
OR
OR
AND

Since z=y, we can feed and multiply y to (x1+x2)

Source: https://youtu.be/L6inc7b9Q8Q?feature=shared
 6. Given this input values, determine and complete the state table:

Present State Next State

Stable/Unstable
𝑦1 𝑦2 𝑥 𝑦1 𝑦2
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 0 1
1 0 0 0 0
A. Stable, Unstable, Stable, Stable, Unstable
B. Unstable, Unstable, Unstable, Stable, Unstable
C. Unstable, Unstable, Unstable, Stable, Stable
D. Stable, Unstable, Unstable, Stable, Unstable

Answer: D.

SOLUTION:

To determine if the data is stable or unstable, check if the values changed in present and the
next state. The first row of data in the table, y1=0 y2=0 in present state remains the same in
value in the next state so it is stable. The second row data changes from 00 to 01, so it is
unstable. Determining the stability is important in asynchronous sequential circuit as unstable
state is considered incorrect output.

SOURCE: https://www.studocu.com/row/document/university-of-zimbabwe/digital-
logics/chapter-4-asynchronous-sequential-circuits-new/93402219
 7. Given the data below, determine its correct transition table

Stable
Next
Present State or O/P
State
Unstable
𝑥1 𝑥2 𝑦 Y S/US Z
0 0 0 0 S 0
0 0 1 0 US -
0 1 0 0 S 0
0 1 1 1 S 1
1 0 0 0 S 0
1 0 1 1 S 1
1 1 0 1 US -
1 1 1 1 S 1

A. B. C.

D.

Answer: D.
SOLUTION:

First step is to make a table of 4x2 and put the combination of x1 and x2 values on one side
and a 1 and 0 for y value. Remember that 11 always comes first before 10 in table
arrangement. Refer to the table below.

Then put the values of Y (those in blue box) inside the table.
 Then encircle the ones who are stable. So the correct answer is:

SOURCE: https://www.youtube.com/watch?v=nYznG7GnlY0

8. An asynchronous sequential circuit is described by the following equations:

𝑦1′ = 𝑥 + 𝑦2
𝑦2′ = 𝑥ˉ ⋅ 𝑦1

Where:

 𝑥= input variable

 𝑦1 , 𝑦2 = internal state variables

1. Determine the stable states for each value of 𝑥.

2. Identify any race conditions.

To construct state table, complete first the initial information. List all the possible values of x, y1,
and y2. Then substitute these values to the given equation for y1’ and y2’ to determine its
possible next value. Combine the outcome of y1’ and y2’. Determine if the Present value (y1y2)
and Next value (y1’y2’) is the same to classify if its stable or unstable.

𝑥 𝑦1 𝑦2 𝑦1′ = 𝑥 + 𝑦2 𝑦2′ = −𝑥 ∗ 𝑦1 Next (𝑦1 ′𝑦2 ′) State

0 0 0 0+0=0 1*0=0 00 Stable
0 0 1 0+1=1 1*0=0 10 Unstable
0 1 0 0+0=0 1*1=1 01 Unstable
0 1 1 0+1=1 1*1=1 11 Stable
1 0 0 1+0=1 0*0=0 10 Unstable
1 0 1 1+1=1 0*0=0 10 Unstable
1 1 0 1+0=1 0*1=0 10 Stable
1 1 1 1+1=1 0*1=0 10 Unstable

To determine if there is any race, there should be more than one state variable changes
simultaneously. Ex. 01 -> 10

Only transition 01 → 10 has a race condition because both bits change at once.

SOURCE: https://www.studocu.com/row/document/university-of-zimbabwe/digital-
logics/chapter-4-asynchronous-sequential-circuits-new/93402219

ARCEO, ZHARMAINE L.

Microprocessor Unit

1. A microprocessor is best described as:

A. A storage device
B. A CPU on a single chip
C. A secondary memory
D. An input device

Answer: B

2. The primary function of the ALU is to:

A. Fetch instructions
B. Store data
C. Perform arithmetic and logical operations
D. Manage I/O
Answer: C

3. Which one of these is NOT a main part of a microprocessor?

A. Control Unit
B. ALU
C. Register array
D. Hard disk

Answer: D

4. Which addressing mode contains the operand inside the instruction itself?
A. Register addressing
B. Immediate addressing
C. Direct addressing
D. Indirect addressing

Answer: B

5. Which architecture style uses many complex instructions, often variable length,
and more addressing modes?
A. RISC
B. Harvard
C. Von Neumann
D. CISC

Answer: D
6. A 16-bit microprocessor has which characteristic?
A. 16-bit address bus always
B. 16-bit data bus (commonly)
C. Only 16 registers
D. Cannot access memory >64KB

Answer: B

7. Which register pair in 8086 contains the segment base for stack operations?
A. CS:IP
B. DS:SI
C. SS:SP
D. ES:DI
Answer: C

8. Which flag indicates the result of the last arithmetic operation was zero?
A. Carry flag
B. Sign flag
C. Parity flag
D. Zero flag

Answer: D

9. In 8086 segmented addressing, physical address =

A. CS + IP
B. CS × 16 + IP
C. DS × 16 + Offset
D. (Segment × 16) + Offset

Answer: D

10. Which of the following is an address generation unit used to calculate effective
addresses?
A. ALU only
B. BIU only
C. AGU (Address Generation Unit)
D. MAR only

Answer: C
Sources: Sanfoundry

11. What does 'opcode' refer to?

A. Operand code address
B. Only registers used by instruction
C. Operation code — the part of an instruction that specifies the operation
D. Memory address of data

Answer: C

12. What is the function of the Stack Pointer (SP)?

A. Points to current instruction
 B. Points to top of stack in memory
C. Both A and B
D. Neither A nor B

Answer: B

13. Which addressing mode accesses memory by adding a base register and an
index register?
A. Immediate
B. Indexed (or Base+Index)
C. Direct
D. Register

Answer: B

14. Parity flag indicates:

A. Negative result
B. Overflow
C. Whether the number of 1s in the result is even or odd
D. Carry out of MSB

Answer: C

15. Which of these is a characteristic of Harvard architecture?

A. Single memory for instructions and data
B. Separate memories (or buses) for instructions and data
C. No program counter
D. Used only in PCs

Answer: B

16. An instruction that does nothing is called:

A. MOV
B. HALT
C. NOP (No Operation)
D. JMP

Answer: C
 17. Which device asserts an interrupt request to get CPU attention?
A. ALU
B. Peripheral (e.g., timer, keyboard)
C. Cache
D. Stack

Answer: B

18. Which of the following is NOT a microprocessor family member from Intel?
A. 8085
B. 8086
C. ARM7
D. 80386

Answer: C

19. Which instruction is used to place a value on the stack?

A. POP
B. PUSH
C. JMP
D. CALL

Answer: B

20. Which bus is used to carry control and timing signals (like read/write, clock)?
A. Data bus
B. Address bus
C. Control bus
D. Interrupt bus

Answer: C

Source: IncludeHelp
Angelo James M. Abuel

Memory Subsystem

1.Which of the following is true about a microprocessor?

A) It is a programmable device that processes digital data

B) It does not require external memory to function

C) It has an inbuilt RAM and ROM

D) It is only used in embedded systems

ANSWER: A

2. What is the primary function of the ALU in a microprocessor?

A) To decode instructions

B) To execute arithmetic and logical operations

C) To control memory access

D) To store program instructions

ANSWER: B

3. In an 8085 microprocessor, how many address lines are available?

A) 8

B) 16

C) 32

D) 64

ANSWER: B

4. The clock speed of microprocessor is measured in:

A) Bytes

B) Hertz

C) Meters per second

D) Cycle per minute

ANSWER: B
5. Which registers in the 8086 microprocessor is used for stack operations?

A) AX

B) CX

C) SP

D) BP

ANSWER: C

6. What is the role of the instruction register in a microprocessor?

A) To store the address of the next instruction

B) To store the currently executing instruction

C) To perform arithmetic operations

D) To store temporary data

ANSWER: B

7. Which architecture does the 8051 Microcontroller follow?

A) Harvard architecture

B) Von Neumann architecture

C) RISC architecture

D) CISC architecture

ANSWER: A

8. What is the size of the general-purpose registers in the 8085 micro-processor?

A) 4-bit

B) 8-bit

C) 16-bit

D) 32-bit

ANSWER: B

9. Which of the following is an example of a microcontroller?

A) Intel 8086
B) ARM Cortex-M3

C) AMD Ryzen 5

D) Intel Pentium

ANSWER: B

10. The program counter (PC) in a microprocessor:

A) Holds the instruction being executed

B) Points to the next instruction to be executed

C) Stores data temporarily

D) Controls input and output operations

ANSWER: B

11. Select the statement that best describes Read-Only Memory (ROM).

A) Nonvolatile, used to store information that changes during system operation

B) Nonvolatile, used to store information that does not change during system operation

C) Volatile, used to store information that changes during system operation

D) Volatile, used to store information that does not change during system operation

ANSWER: B

12. Dynamic memory cells store a data bit in a______

A. Diode

B. Resistor

C. Capacitor

D. Flip-flop

ANSWER: C

13. A major disadvantage of the mask ROM is that it:

A) Is time consuming to change the stored data when system requirements change

B) Is very expensive to change the stored data when system requirements change

C) Cannot be reprogrammed if stored data needs to be changed

D) Has an extremely short life expectancy and requires frequent replacement

ANSWER: C

14. In general, the have the smallest bit size and the have the largest.

A) EEPROMs, Flash

B) SRAM, mask ROM

C) mask ROM, SRAM

D) DRAM, PROM

ANSWER: A

15. In a DRAM, what is the state of R/W during a read operation?

A) Low

B) High

C) Hi-Z

D) None of the above

ANSWER: B

16. If memory chip size is 256 x 1 bits, the number of chips required to make 1 k byte memory
is:

A) 8

B) 12

C) 24

D) 32

ANSWER: D

17. A microprocessor with a 16-bit address bus is used in a linear memory selection
configuration (i.e., Address bus lines are directly used as chip selects of memory chips) with 4
memory chips. The maximum addressable memory space is:

A) 64 K

B) 16 K

C) 8 K
D) 4 K

ANSWER: A

18. The remaining address line of ______ bus is decoded to generate chip select signal.

A) Data

B) Address

C) Control bus

D) Both (a) and (b)

ANSWER: B

19. The memory segment registers in 8086 are denoted by:

A) AS, BS, CS, DS

B) BS, CS, SS, ES

C) CS, DS, SS, ES

D) DS, ES, FS, SS

ANSWER: C

20. The work of EU in 8086 MPU is:

A) Encoding
B) Decoding
C) Processing
D) Calculations

ANSWER: B

MADLANGSAKAY NEIYAH

I/O SUBSYSTEM

1. If one or more devices use a common set of wires to communicate with the computer
system, the connection is called ______

a) CPU

b) Monitor
c) Wirefull

d) Bus

Answer: d

2. The _________ present a uniform device-access interface to the I/O subsystem, much as
system calls provide a standard interface between the application and the operating system.

a) Devices

b) Buses

c) Device drivers

d) I/O systems

Answer: c

3. A ________ is a collection of electronics that can operate a port, a bus, or a device.

a) controller

b) driver

c) host

d) bus

Answer: a

4. An I/O port typically consists of four registers status, control, ________ and ________
registers.

a) system in, system out

b) data in, data out

c) flow in, flow out

d) input, output

Answer: b

5. The ______ register is written by the host to send output.

a) status

b) control

c) data in
d) data out

Answer: d

6. The hardware mechanism that allows a device to notify the CPU is called _______

a) polling

b) interrupt

c) driver

d) controlling

Answer: b

7. The CPU hardware has a wire called __________ that the CPU senses after executing every
instruction.

a) interrupt request line

b) interrupt bus

c) interrupt receive line

d) interrupt sense line

Answer: a

8. The _________ determines the cause of the interrupt, performs the necessary processing
and executes a return from the interrupt instruction to return the CPU to the execution state
prior to the interrupt.

a) interrupt request line

b) device driver

c) interrupt handler

d) all of the mentioned

Answer: c

REFERENCES: https://www.sanfoundry.com/operating-system-mcqs-application-io-interface-1/

Application I/O Interface

9. The interrupt vector contains ____________

a) the interrupts
b) the memory addresses of specialized interrupt handlers

c) the identifiers of interrupts

d) the device addresses

Answer: b

10. For large data transfers, _________ is used.

a) dma

b) programmed I/O

c) controller register

d) none of the mentioned

Answer: a

11. A character stream device transfers ____________

a) bytes one by one

b) block of bytes as a unit

c) with unpredictable response times

d) none of the mentioned

Answer: a

12. A block device transfers ____________

a) bytes one by one

b) block of bytes as a unit

c) with unpredictable response times

d) none of the mentioned

Answer: b

13. What is a dedicated device?

a) opposite to a sharable device

b) same as a sharable device

c) can be used concurrently by several processes

d) none of the mentioned

Answer: a

14. A keyboard is an example of a device that is accessed through a __________ interface.

a) block stream

b) set of blocks

c) character stream

d) none of the mentioned

Answer: c

15. In polling ____________

a) busy – wait cycles wait for I/O from device

b) interrupt handler receives interrupts

c) interrupt-request line is triggered by I/O device

d) all of the mentioned

Answer: a

REFERENCES: https://www.sanfoundry.com/operating-system-mcqs-application-io-interface-2/

Kernel I/O Subsystems

16. Buffering is done to ____________

a) cope with device speed mismatch

b) cope with device transfer size mismatch

c) maintain copy semantics

d) all of the mentioned

Answer: d

17. Caching is ________ spooling.

a) same as

b) not the same as

c) all of the mentioned

d) none of the mentioned

Answer: b

18. Caching ____________

a) holds a copy of the data

b) is fast memory

c) holds the only copy of the data

d) holds output for a device

Answer: a

19. Spooling ____________

a) holds a copy of the data

b) is fast memory

c) holds the only copy of the data

d) holds output for a device

Answer: c

20. The ________ keeps state information about the use of I/O components.

a) CPU

b) OS

c) kernel

d) shell

Answer: c

21. A ________ is a full duplex connection between a device driver and a user level process.

a) Bus

b) I/O operation

c) Stream

d) Flow

Answer: c
22. I/O is a _________ in system performance.

a) major factor

b) minor factor

c) does not matter

d) none of the mentioned

Answer: a

23. If the number of cycles spent busy – waiting is not excessive, then ____________

a) interrupt driven I/O is more efficient than programmed I/O

b) programmed I/O is more efficient than interrupt driven I/O

c) both programmed and interrupt driven I/O are equally efficient

d) none of the mentioned

Answer: b

REFERENCES: https://www.sanfoundry.com/operating-system-mcqs-kernel-io-subsystems/

24. which of the following computer memories is fastest?

a. Cache

b. Primary

c. Mass storage

d. Off-line back up

Answer: a

25. Polling is the method used for:

a. determining the state of a microprocessor

b. establishing communication between CPU and a peripheral

c. establishing a priority for communication with several peripherals

d. determining the next instruction

Answer: b
26. The technique of assigning a memory address to each I/O device in the computer system is
called:

a. memory - mapped I/O

b. ported I/O

c. dedicated I/O

d. Wired I/O

answer: a

27. The process of jointly establishing communication is called.

a. DMA

b. bidirectional addressing

c. Multiplexing

d. Handshaking

answer: a

REFERENCES: https://pinoybix.org/2024/06/mcq-in-microprocessor-part-1-engineering-board-
exam.html
28. Which method bypasses the CPU for certain types of data transfer?

a. Software interrupts

b. Interrupt-driven I/O

c. Polled I/O

d. Direct memory access (DMA)

answer: d

REFERENCES:https://www.syedengg.ac.in/pdf/TechnicalBooklet/ECE/MICROPROCESSOR%20AN
D%20MICROCONTROLLER/MultipleChoiceQuestionson8086Microprocessor.pdf