GSM/DCS1800 Dual Band Direct-Conversion Transceiver IC With a DC Offset Calibration System

Satoshi Tanaka, Taizo Yamawaki, Kumiko Takikawa, Norio Hayashi, Ikuo Ohno, Tetsuya Wakuta, Satoru Takahashi and Masumi Kasahara Hitachi, Ltd., Satoshi@crl.hitachi.co.jp Abstract
GSM/DCS1800 direct-conversion transceiver IC with on-chip DC offset calibration system is fabricated on a 0.35 m SOI BiCMOS process. The IC achieves 107.7 /-19.5 dBm (GSM) and -105.7 /-28.5 dBm (DCS) reference sensitivity and AM suppression performance, respectively, with 112 mA current and 2.8V power supply voltage on receiving mode.

Bob Henshaw TTP Communications Ltd. bob.henshaw@ttpcom.com

adjacent channel blocking signals are removed by onchipLPF.

BPF RF Input

BPF BB LSI

(a) Super-Heterodyne Receiver

LPF

DC offset BB LSI

1. Introduction
A direct-conversion receiver architecture [5-9] is one of the key techniques for reducing the number of components from RF section of mobile terminals. However, the architecture has some fundamental issues for applying it to the real systems. The biggest issue is DC offset, which is generated by RF front-end circuits and subsequent baseband circuits (amplifier and filters). This paper describes mechanisms of DC-offset generation and proposes a calibration scheme that suppresses the DC offset. The proposed method is applied for GSM/DCS1800 dual-band direct conversion transceiver IC that is fabricated on a 0.35 m SOI BiCMOS process [1]. The IC consists of fully integrated dual band direct-conversion receiver, offset PLL transmitter and synthesisers

RF Input

LPF

(b) Direct-Conversion Receiver

Figure 1 Architecture Comparison

V DC t Over Lange BBLSI Input Lange

+ cos(2 t) C 2 2

2
LPF Out

G 2

cos(Ct)
G BB LSI

Lo Leakage Lo Signal

LPF cos(Ct)

2.

Direct conversion receiver

Figure 2 Impact of DC offset This architecture does not require external filters. However, generation of DC offset becomes major issue. Figure 2 shows impact of DC offset on the directconversion receiver. In Fig. 2, the self-mixing effect is presented as a typical example of DC offset generation mechanism. The local signal leaks to RF signal pass and is reflected to the mixer. This process generates DC offset and blocker whose frequency is twice of the local signal. The bandwidth of GSM baseband signal is less than 100 kHz. For that low-frequency base-band signal, the realisation of DC cut circuit is difficult. Therefore the baseband LPF and a gain stage are connected directly.

Figure 1 shows comparison between a super-heterodyne architecture and a direct-conversion receiver. In case of the super-heterodyne architecture, a received signal is amplified by LNA and after rejecting image signal by RF BPF, the signal is down-converted to IF signal. An IF channel BPF removes adjacent channel blocking signals. The IF signal is amplified to proper level, and finally demodulated to baseband I and Q signals. This architecture requires two external high-Q filers. In case of the direct-conversion architecture, after an RF signal is amplified by LNA, the signal is directly demodulated to baseband I and Q signals. From the I and Q signals,

Although the high frequency blocker signal is removed by LPF, the gain stage circuit amplifies the DC offset which may reach the maximum input range of ADC on the baseband LSI. Even though the DC offset of only 1mV at mixer output is assumed, the output DC offset level reaches 1V with a 60-dB gain stage. Some DC offset calibration scheme is required for the direct conversion receiver.

4.

DC offset generation mechanisms

3.

DC offset calibration scheme

DC offset

DC offset calibration error G E

Calibration

E G BBLSI ADC

G DAC ADC

DAC

Registe r DC offse t calibration

Registe r DC offse t calibration

Figure 3 Sequential DC offset calibration scheme Figure 3 shows a proposed sequential DC offset calibration scheme. Each gain stage has its own DC offset calibration circuit consisting of ADC, register and DAC. The calibration process starts from the first stage and is executed sequentially. Therefore calibration errors of preceding stage is calibrated by the subsequent stage. Figure 4 shows the advantage of proposed calibration method. Here, the circuit gain of 512(54dB), and input DC offset of 25mV are assumed. Input DC offset of 25mV is amplified by the 54-dB amplifier, then (ignoring saturation of the circuit) the output DC offset reaches 12.8V. For reducing the output DC offset level of gain stages to 6mV, a 12-bit resolution calibration system is required if only one calibrating system is applied to whole gain stages. However, if each stage has its own calibration system, 6-bit resolution is enough for the above target. The sequential calibration scheme does not require fine resolution circuit and easy to apply on the real systems.
Single Calibration(12bit) Calibration Error [mV]
Input DC offset 25mV

As mentioned in the previous sections, DC offset from an RF front-end circuit is key issue for the direct conversion receiver. In this section, three major factors for DC offset generation, i.e. self-mixing effect, duty cycle error of local signal and miss matching of load resistor are presented and the countermeasure for those phenomena is discussed. Figure 5 (a) shows the selfmixing effect. If the local signal leaks to RF signal pass, the leaked local signal is down converted to DC signal. For reducing this effect, balanced local signal pass and balanced RF signal pass is applied. The leak level strongly depends on the RF input source impedance of the mixer. For avoiding the impact of RF input source impedance variation, a buffer amplifier is inserted between the LNA and Mixer. Figure 5 (b) shows the impact of local signal duty cycle on the current of the mixer. If the local signal keeps 50% duty cycle, the current offset is cancelled at the output of the mixer even when the input stage circuit of the mixer has DC offset current IUB. However if the duty cycle loses its balance, DC offset is generated from the mixer. To achieve 50 %-duty cycle, a high CMRR amplifier is applied for Lo buffer circuit.

LNA Buff. RF

MIX BB Static DC offset Lo

(a) Self mixing

I+

T2 IUB T1 + T2
T1 T2 T2 I

I+
T1

T1 IUB T1 + T2

I+IUB

(b) Lo signal duty cycle

103 102 Calibration 10 6 1 0 56 10 12 15
Single Se que ntial Calibration

X512
DC C

R I+IB RF Vdiff

R+R I+IB

Sequential Calibration(6 bit)

Vdiff = RI + RI B
Dynamic DC offset Static DC offset

X8
25mV

X8

X8

DC C DC C DC C DC CDC offset Calibration Circuit

Resolution of ADC [bit]

(c) Miss matching of load resistors Figure 5 DC offset on front-end circuits

Figure 4 Advantage of the proposed calibration scheme

Dynamic DC offset (V)

80 60 40 20 0 -50 -45 -40 -35 -30 Input Level (dBm) -25 -20 GSM DCS1800

(d) Measured dynamic DC offset Figure 5 Continued Figure 5 (c) shows the impact of the miss matching of load resistors. There are two types of DC offset that is generated from front-end circuit. One is the static DC offset and the other is dynamic DC offset. The static DC offset is independent of input signal level, generated by self-mixing effect, duty cycle error and load resistor miss matching. Measured static DC offset of the front-end circuits for GSM is 600 V and that for DCS1800 is 700 V. The static DC offset can be cancelled out by the calibration scheme presented in the previous section. The dynamic DC offset can be observed when the bias current is increased by a large input signals with existence of resistor miss matching. The dynamic DC offset depends on the input signal level and degrades AM suppression performance. This phenomenon can not be cancelled by the calibration scheme so that it must be small enough. For reducing dynamic DC offset, the error of load resistors must be small enough by careful layout. Figure 5 (d) shows measured dynamic DC offset of RF front-end circuit. For both GSM and DCS1800, the dynamic offset below 30 dBm input is less than 20V.

(for GSM and DCS1800), and multi-stage baseband circuits. The baseband circuit consists of low-pass filters (LPF) and programmable gain amplifiers (PGA). The filters and amplifiers are cascaded alternatively for achieving both low-noise performance and low distortion performance. 90 degree out-of-phase local signals for GSM (925-960 MHz) are generated from 3700-3840 MHz RF-VCO signal, by divide-by-4 circuits. Those for DCS (1805-1880 MHz) are generated from 3610-3760 MHz RF-VCO signal, by divide-by-2 circuits. A synthesiser for the RF VCO and a complete IF PLL circuit are also integrated. For transmitting circuit, the offset phase locked loop circuit scheme is applied [2-3].

RPT

RNT 2-Layer polycrystalline resistor

Figure 7 Sallen-Key type LPF Circuit Simple CR active filters as shown in Fig. 7 are applied for base band channel filters. One of the features of the process is 2-layer polycrystalline resistor [4] which have zero temperature coefficients. The resistor consists of different polycrystalline resistors RPT and RNT. RPT has positive temperature coefficient, RNT has negative coefficient and tow features cancel each other. With those resistors, the frequency response of a simple CR actives filter does not depend on temperature. With this 2-layer polycrystalline, high-Q channel filter can be realised on the chip without applying complicated gm-C filter and auto frequency adjust systems,

5.

Transceiver architecture
MIX
2

925~960 MHz LNA 1805 ~1880MHz

PGA

I Q

PGA

6.
12 10 RBER (%)

Measured result
GSM DCS1800

RF f ilter RF f ilter

LNA

RF PLL Synt h.
2 2 2

IF PLL Synt h.

S/W LPF LPF

RF VCO 3610 3760MHz 3700 3840MHz

8 6 4 2 0 -40

GSM

DCS1800

GSM

DCS 1800

I 880~915MHz 1710~1785MHz PA Module TX VCO Loop f ilter Phase Detector

2

-35

Figure 6 Transceiver Block Diagram Figure 6 shows a block diagram of the transceiver IC. The receiver consists of 2 sets of RF front-end circuits

-30 -25 -20 Bloker Level (dBm) Figure 8 AM suppression test

-15

Figure 8 shows the measurement result of an AM suppression test. The required performance is that a

residual bit error rate (RBER) should be less than 2 % with 99-dBm wanted signal and 31-dBm unwanted signal which start during the receiving burst for both GSM and DCS. Both performances achieve GSM specification. However, because of lower dynamic DC offset level (see. Fig. 5 (d)), the GSM performance is better than that of DCS1800.
12 11 10 9 8 7 6 5 4 3 2 1 0

7.

Acknowledgement

The authors would like to thank to M. Hotta, K. Watanabe, and T. Hongo of Hitachi, Ltd., J. Hildersley and D. Freeborough of TTP Communications Ltd for their discussion support and constant encouragement.

GSM DCS1800

RBER (%)

LNA & Mixer

PGA & Filters

-112 -110 -108 -106 -104 -102 -100 -98 -96

-94 -92 -90

Input Signal Level (dBm)

Figure 9 Sensitivity test Figure 9 shows the measurement result of a reference sensitivity test. The required performance is defined by a RBER which should be less than 2 % with 102 dBm wanted signal. On GSM mode, the test chip achieves 107.7 dBm, and on DCS mode it achieves 105.7 dBm. For the above two testing conditions, the loss and offband suppression of an antenna switch and an RF band pass filter is included. Table 1 shows a performance summary of the test chip. The total current on receiving mode is 112mA and that on transmitting mode is 61mA. 18.5 dBm (-19.6 dBm) of 3 MHz blocking characteristics for GSM (DCS1800) is achieved. Figure 10 shows a chip photograph. The chip size is 3.4x3.4mm2 and the chip is mounted on a QFP-56 plastic package. For both GSM and DCS1800 the test chip achieves sufficient performance. Table 1 Total performance
Process Technology Package Chip Size Current Consumption Reference Sensitivity level 3 MHz Blocking Characteristics AM Suppression Characteristics Receiver Transmitter GSM(<-102 dBm) DCS(<-102 dBm) GSM(>-23 dBm) DCS(>-26 dBm) 0.35mm SOI Bi-CMOS QFP-56 3.4x3.4mm 2 112 mA 61mA -107.7 dBm -105.7 dBm -18.5 dBm -19.6 dBm -19.5 dBm -28.5 dBm I:21mV, Q:39mV

MOD & OPLL

Synth.

Figure 10 Chip Photograph

8.

References

GSM(>-31 dBm) DCS(>-31 dBm) I and Q Output DC offset Level

[1] K. Takikawa et. al. RF circuit technique of dualband transceiver IC for GSM and DCS1800 applications, IEEE, Proceedings of the 25th ESSCIRC 1999 pp.278-281. [2] T. Yamawaki et. al., "A 2.7-V GSM RF Transceiver IC", IEEE JSSC, Vol.32, No.12, Dec. 1997 pp. 2089-2096. [3] T. Yamawaki et. al, "A Dual-band Transceiver for GSM and DCS1800 applications, , IEEE, Proceedings of the 24th ESSCIRC 1998 pp.48-49. [4] H. Shimamoto et. al. Development of accurate 2layer polycrystalline silicon film resistor (1), Proc. IEICE Fall Conf., C-452, 1994 [5] S. Atkinson and J. Strange, A novel approach to direct conversion RF receivers for TDMA applications, MWE99 Microwave Workshop Digest, 1999 pp. 53-57. [6] A. A. Abidi, Direct-Conversion Radio Transceivers for Digital Communications, IEEE JSSC, Vol. 30, No. 12, Dec.1995. pp1399-1410. [7] B. Razavi, RF Microelectronics, PrenticeHall PTR 1998. [8] F. O. Eynde, J. Craninckx and P. Geoetschalckx, A Fully-Integrated Zero-IF DECT Transceiver, IEEE ISSCC Digest of Tech. Papers 2000, pp138-139. [9] A. Jayaraman et. al. A Fully Integrated Broadband Direct-Conversion Receiver for DBS Applications, IEEE ISSCC Digest of Tech. Papers 2000, pp140-141.