Professional Documents
Culture Documents
Introducción
Registros de almacenamiento. Banco de registros
Registros de desplazamiento
Contadores asíncronos
Contadores síncronos
Contadores módulo N
Registros y Contadores
Schematic Shape
171
Q3 9
12 CLK
Q3 10
13 CLR
Q2 7
Q2 6
11 D3 Q1 2
5 D2 Q1 3
4 D1 Q0 1
14 D0 Q0 15
Q1 Q2 Q3 Q4
1 0 0 0
Shift
0 1 0 0
Shift
0 0 1 0
Shift
0 0 0 1
Preset control
Shift pulse
Clear control
(a)
Preset control
Shift pulse Shift pulse
Clear
Serial A
inputs B
Clock
QA
QB
QC
Outputs QD
QE
QF
QG
Clear Clear
(b)
Registros de Desplazamiento
Registros de Desplazamiento SIPO
Registros de Desplazamiento
Conversión de Paralelo a Serial
Parallel Parallel
Inputs Outputs
Serial
transmission
• Implementación:
• La entrada de reloj al contador se conecta a las
entradas de reloj de todos los biestables
• La entradas de datos (J-K ó T) del biestable de
menor peso se conecta a un “1” fijo
• Se precisan puertas adicionales para implementar
la lógica que indique cuando deben voltear su
estado los biestables
Contadores Síncronos: Ejemplo
Contadores Módulo N
1 Pulse/hour 1 Pulse/minute
¸6 ¸ 10 ¸6 ¸ 10
Clear
Start/Stop
¸5 ¸ 12
Pulse
generator 1 Pulse/second
Power line
Counter Design Procedure
Introduction
This procedure can be generalized to implement ANY finite state
machine
This is called
"Remapping the Next
State Function"
Counter Design Procedure
Example Continued
0 1 1 1 1
1 1 1 1 1 QA QB QC
TS Q T S Q T S Q
B CLK Q CLK Q CLK Q
TA = 1 R R R
\Reset
C
CB
Count
A 00 01 11 10
0 0 0 0 0
Timing Diagram:
1 1 1 1 1
100
B
TB = A \Reset
CB
C QC
A 00 01 11 10
QB
0 0 0 0 0
QA
1 0 1 1 0
Count
B
TC = A • B
Counter Design Procedure
More Complex Count Sequence
Toggle Excitation
Table
TC = A C + A C = A xor C
TB = A + B + C
TA = A B C + B C
Counter Design Procedure
More Complex Counter Sequencing
Resulting Logic:
5 Gates
10 Literals +
Flipflop connections
Timing Waveform:
100
Count
\Reset
0 0 0 0 1 1 0
C
B 0 0 1 1 0 1 0
A 0 0 0 1 1 0 0
Self-Starting Counters
Start-Up States
At power-up, counter may be in any possible state
Self-Starting Solution:
Design counter so that even the invalid states
eventually transition to valid state
RS Excitation Table
1 1
RC SC RC =
CB CB SC =
A 00 01 11 10 A 00 01 11 10
0 0 RB =
1 1 SB =
RB SB RA =
CB CB SA =
A 00 01 11 10 A 00 01 11 10
0 0
1 1
RA SA
Implementation with Different Kinds of FFs
RS FFs Continued
RC = A
SC = A
RB = A B + B C
SB = B
RA = C
SA = B C
Implementation with Different Kinds of FFs
RS FFs Continued
C B A
\A R Q RB R Q C R Q
CLK CLK CLK
A S Q \B S Q SA S Q
\C \B \A
Count
A
RB B SA
C
B \C
1 1
JC =
JC KC
KC =
CB CB
A 00 01 11 10 A 00 01 11 10
JB =
0 0
1 1
KB =
JB KB JA =
KA =
CB CB
A 00 01 11 10 A 00 01 11 10
0 0
1 1
JA KA
Implementation with Different Kinds of FFs
J-K FFs Continued
JC = A
KC = A
JB = 1
KB = A + C
JA = B C
KA = C
Implementation with Different Kinds of FFs
J-K FFs Continued
+
C B A
A J Q J Q JA J Q
CLK CLK CLK
\A K Q KB K Q C K Q
\C \B \A
Count
A B JA
C KB \C
DC = A
DB = A C + B
DA = B C
C B A
A D Q DB D Q DA D Q
\C
DB B
\A \C DA
\B
But yielded worst gate and literal count for this example!
Tend to yield best choice for packaged logic where gate count is key
also a function
of the T Enable
Downstream stages
lag in their 1111 to
0000 transitions
D C B A
Clock
Load
R Q Q QQ D
1 C D CBA L C
6 O C O C
3 L B
A L
P T K DCBA D R A
+ + Load 0 1
Use RCO signal to trigger Load of a new state
0110
is the state Since 74163 Load is synchronous, state changes
to be loaded only on the next rising clock edge
Asynchronous vs. Synchronous Counters
Offset Counters Continued
Ending Offset Counter:
e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
CLR
D C B A
1
0
Decode state to
determine when to Replace '163 with '161, Counter with Async Clear
reset to 0000 Clear takes effect immediately!
Moore and Mealy Machine
Definitions
State
Register
Moore Machine
Xi Combinational
Comb. Outputs are function
Inputs Logic for
Logic for
solely of the current
state
Outputs
Next State
(Flip-flop Zk
Outputs change
Inputs) Outputs
Mealy Machine
Xi Zk
Combinational Outputs
Outputs depend on
Inputs
Logic for
Outputs and state AND inputs
Next State
Input change causes
State an immediate output
State Register Clock Feedback
change
Asynchronous outputs
Moore and Mealy Machine
State Diagram Equivalents
Moore N D + Reset
Reset/0
(N D + Reset)/0
Mealy
Machine Reset
0¢ 0¢ Machine
[0]
Reset Reset/0
N N/0
5¢ 5¢
ND D N D/0 D/0
[0]
N N/0
10¢ 10¢
D D/1
[0] ND N D/0
N+D N+D/1
15¢ 15¢
[1] 1
F F
T T
F F
T T
F Equivalent
ASM Charts
Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
no change
Block Diagram N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset FSM Mechanism
Clk
Vending Machine Example
Step 2. Map into more suitable abstract representation
Output: open N D
D N
S3 S4 S5 S6
S7 S8
[open] [open]
Vending Machine Example
Step 3: State Minimization
Present Inputs Next Output
Reset
0¢
State D N State Open
0¢ 0 0 0¢ 0
N 0 1 5¢ 0
5¢
1 0 10¢ 0
D 1 1 X X
5¢ 0 0 5¢ 0
N 0 1 10¢ 0
10¢ 1 0 15¢ 0
D 1 1 X X
N, D 10¢ 0 0 10¢ 0
15¢
0 1 15¢ 0
1 0 15¢ 0
[open]
1 1 X X
15¢ X X 15¢ 1
reuse states
whenever Symbolic State Table
possible
Vending Machine Example
Step 4: State Encoding
Present State Inputs Next State Output
Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X
Vending Machine Example
Step 5. Choose FFs for implementation
D FF easiest to use
D1 D0 Open
Q1
D D1 Q1
D Q
Q0 CLK \ Q1
RQ
N
\reset
D1 = Q1 + D + Q0 N
N
\ Q0 OPEN
D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
\N
D0 D Q0
Q1
Q OPEN = Q1 Q0
CLK \ Q0
N RQ
Q1 \reset
D
8 Gates
Vending Machine Example
Step 5. Choosing FF for Implementation
J-K FF
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
N
Q0 J Q Q1
D \ Q1
CLK K RQ
\ Q0
N
OPEN
Q1
D Q0
J Q
\ Q1 CLK
\ Q0
KR Q
N
\reset 7 Gates
Problems
X: 11011010010
Z: 00000001000
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
S1 001
H.Z 0
0 1
M
S2 010 S3 011
H.Z 1 H.Z 1
H.Z 0
0
M
1
M
1
0
S6 110
H.Z 2 S4 100
H.Z 1 H.Z 2
1
S7 111 M
H.Z 2 0
H.Z 1
H.Z 0
S5 101
H.Z 2
H.Z 0
0 1
M
0 1
M
Traffic Light Controller
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
Traffic Light Controller
Picture of Highway/Farmroad Intersection:
Farmroad
C
HL
FL
Highway
Highway
FL
HL C
Farmroad
Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal Description
reset place FSM in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired
S0 S3
H.HG H.HR
H.FR H.FY
S1 S2
H.HY H.HR
H.FR H.FG
Traffic Light Controller
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C · TL
S0 S0
H.HG H.HG
H.FR H.FR
C · TL
0 0
TL TL • C
1 1
0
C H.ST
H.ST S1
H.HY
H.FR
S1
H.HY
H.FR
S1 S2
H.HY H.ST H.HR
H.FR H.FG
0 1
TS
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
S0 S3
H.HG H.HR
H.FR H.ST H.FY
0 1 0
TL • C TS
H.ST H.ST
S1 S2
H.HY H.ST H.HR
H.FR H.FG
0 1 0
TS TL + C
1
TS S3: FY
TS/ST
TL + C/ST
S2
TL • C
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2
Digital Combination Lock
Enumeration of states:
START
START entered on RESET
0
Enter
0
1
COMP0
Path to unlock:
N 0
KI = L 0 Enter
Y 1
IDLE0 COMP2
Wait for
Enter Key press
0 N
Enter KI = L2
1 Y
COMP1 DONE
H.Unlock
N 0
Compare Key-IN KI = L1 Reset
Y 1
START
Digital Combination Lock
Now consider error paths
0 0 0
Enter Enter Reset
1 1 1
ERROR1 ERROR2
START
Reset • Enter
Comp0
KI = L0 KI ° L0
Enter Enter
Idle0 Idle0'
Enter Enter
Comp1 Error1
Equivalent State Diagram KI ° L1
KI = L1
Enter
Enter
Idle1 Idle1'
Enter Enter
Comp2 Error2
KI = L2 KI ° L2
Reset Reset
Done Error3
[Unlock] [Error]
Reset Reset
Start Start