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Z80 Instruction Set

Structure of Instructions
Every instruction consists of an operational Code (OP-Code) and -if necessary- an address part for the operand(s).
OP-Code Address(es) Operand(s)

Z80: OP-Code 1 Byte (exceptions: in OPs using index registers the OP-Code is two bytes) the instruction set is not orthogonal
# of addresses: 0 1 2 3 R1 op R2 (A) op R (A1) op (A2) (A1) op (A2) R3 R R (A3)

(A): contents of A, op: binary operation, : transfer, A: address, R: register

Z80 Address Modes (1)


Implied The instruction has only an OP-Code, the register is "implied" in the code Ex: CPL (Complement A): A A, OP-Code 2FH

Register Direct The Instruction has only an OP-Code, both source and destination registers are defined in this code
Ex: LD A,B (Load A with contents of B): A B, OP-Code 78H
Register Indirect The instruction has only the OP-Code, the destination register is defined in this code and a 16Bit register containing the address of the source operand Ex: LD A,(HL) (Load A from address contained in HL): A (HL), 7EH

Z80 Address Modes (2)


Immediate The instruction contains the value of the operand immediately eg LD BC,1000H: BC 1000H, Op-Code 01H 00H 10H eg LD A,1FH: A 1FH, Op-Code 3EH 1FH
OP-Code m 8-bit operand m

OP-Code n m 16-bit operand {m,n}

Extended (Direct) The address of the operad is given as part of the instruction eg LD A,(1000H): A (1000H), OP-Code 3AH 00H 10H

OP-Code n m m n

memory

...
address operand

...

Z80 Address Modes (3)


Relative The address is relative to PC (only for Branches!) eg JR 10H: PC PC + 10H Op-Code 18H 0EH Hint for JR e:
memory -126 e=x+2 0 x: (-128, +127) e: (-126, +129) +129

OP-Code offset

PC next OP-Code

...
PC PC+2 OP-Code (JR) x=e-2 next instruction

...
destination address: (PC + 2) + x = PC + e

Z80 Address Modes (4)


Indexed
The address of the operand is constructed from the index register (all instructions with index registers have 2 byte OP-Codes!) eg LD A,(IX + 10H): A (IX + 10H,) Code DDH 7EH 10H
OP-Code1 OP-Code2 dislpacement d d: signed 8-bit (-128, +127) IX or IY sign extended d operand

...
operand

...

Z80 Address Modes (5)


Modified Page Zero A fixed address correspondence only used for the restart instruction eg RST 20H: Stack PC, PCH 00H, PCL 20H, OP-Code E7H
t p

t 100 101 110 111

p 20H 28H 30H 38H

RST p: Opcode 11 t 111 B with:

000 001 010 011

00H 08H 10H 18H

Bit

Direct addressing of a bit for bit manipulations eg SET 3,A (Set bit 3 of A to 1): A3 1, OP-Code CBH DFH (SET b,A: Ab 1, OP-Code CBH 11 b 111B)

Z80 Address Modes (6)


I/O Addressing Only with special I/O commands (IOREQ = 1, MREQ = 0) Ex: IN A,(10H): A (n), OP-Code DBH 10H
Hint (A7, ..., A0) n and (A15, ..., A8) A By loading A before using an I/O instruction the available space for I/O-addresses can be extended

Sample Line from Instruction Set Listing


Mnemonic ADD A,(HL) IN A,(n) Symbolic Operation A A+(HL) A (n) Flags S Z H X X X X P/V N C V 0 Opcode 76 543 210 10 000 110 11 011 011 n Hex 86 DB ...

...

# of Bytes 1 2

# of M Cycles 2 3

# of T states 7 11

Comments n to A0 A7 Acc. to A8 A15

Instruction Classes
Data Transfer Group Arithmetic Group Logical and Rotate Group Branch Group Stack, I/O, and Machine Contol Group Exchange, Block Transfer, and Search Group Bit Manipulation Group

Data Transfer Group


Symbolic Mnemonic Description Operation LD A,B AB place a copy of B in A LD HL,0700H HL 0700H load HL with 0700H load IX with the contents of memory DD 2A 00 07 LD IX,(0700H) IX (0700H) starting at location 0700H *
* Low Address (0700H) = Least Significant Byte (LSB) High Address (0701H) = Most Signifikant Byte (MSB)

OP Code Hex 78 21 00 07

Arithmetic Group

OP Code Hex 80 09

Mnemonic ADD A,B

Symbolic Operation AA+B

Description

B is added to A, result in A BC is added to HL, ADD HL,BC HL HL + BC result in HL

Logic and Rotate Group


OP Code Symbolic Mnemonic Hex Operation
A0 AND B Description

BE

CP (HL)

Bitwise AND-operation of A A B A and B, result in A the contents of the memory location A - (HL) addressed by HL is subtracted from A, set flags, A unchanged

OP Code Hex C3 00 01 30 (e-2)

Branch Group Symbolic Mnemonic


Operation JP 0100H JR NC,0100H PC 0100H PC PC + e (SP-1) PCh * (SP-2) PCl * PC 0100H SP SP - 2 PCl (SP) * PCh (SP+1) * SP SP + 2
*

Description

control is tranferred to address 0100H control is transferred to address in PC + offset e if Carry-Flag is 0 control is transferred to subroutine at address 0100H, return address is stored on stack, SP is decremented by 2 control is transferred to address on top of stack (return address), SP is incremented by 2

CD 00 01

CALL 0100H

C9

RET

PCh/l: high/low order byte of PC

Stack, I/O, and Machine Control Group


OP Code Hex
C5 Mnemonic PUSH BC

C1

POP BC

Symbolic Operation (SP-1) B (SP-2) C SP SP - 2 C (SP) B (SP+1) SP SP + 2

Description BC is copied to top of stack, SP is decremented by 2 top of stack is copied to BC, SP is incremented by 2

Exchange, Block Transfer, and Search Group


OP Code Hex
D9 Mnemonic EXX

ED B8

LDDR

Symbolic Operation BC B'C' DE D'E' HL H'L' (DE) (HL) DE DE - 1 HL HL - 1 BC BC - 1


A - (HL) HL HL + 1 BC BC - 1

Description exchange of primary and alternative general purpose registers load location (DE) with location (HL), decrement DE, HL, and BC, repeat until BC = 0 compare location (HL) with accumulator, increment HL, decrement BC, set flags, A unchanged

ED A1

CPI

Bit Manipulation Group


OP Code Hex CB 61 CB 74
CB 97 Mnemonic BIT 4,C SET 6,H RES 6,H

Symbolic Operation Z C4 * H6 1 *
H6 0 *

Description test bit 4 of C, set Z flag set bit 6 of H to 1 set bit 6 of H to 0

the Index at the register denotes the bitpostion in that register

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