EKT 441

MICROWAVE COMMUNICATIONS
CHAPTER 6:
MICROWAVE AMPLIFIERS

INTRODUCTION
Most RF and microwave amplifiers today used transistor devices
such as Si or SiGe BJTs, GaAs HBTs, GaAs or InP FETs, or GaAs
HEMTs.
Microwave transistor amplifiers are rugged, low cost, reliable and
can be easily integrated in both hybrid an monolithic integrated
circuitry.

General Amplifier Block Diagram

DC supply

vs(t)

vi(t)
ii(t)

Zs

Input
Matching
Network

Amplifier

vo(t)

Output
Matching
Network

Pin
Vcc

Vs

io(t)

PL
ZL

The active
component
Input and output voltage relation of the amplifier
can be modeled simply as:
vo t a1vi t a2vi 2 t a3vi3 t H .O.T .
3

Amplifier Classification

Amplifier can be categorized in 2 manners.

According to signal level:
Small-signal Amplifier.
Our approach in this chapter
Power/Large-signal Amplifier.
According to D.C. biasing scheme of the active component:
Class A.
Class B.
Class AB.
Class C.
There are also other classes, such as Class D (D stands for
digital), Class E and Class F. These all uses the transistor/FET as
a switch.
4

Small-Signal Versus Large-Signal Operation

Usually non-sinusoidal waveform

Large-signal: vo t a1vi t a2vi 2 t a3vi 2 t H .O.T .

Nonlinear

Small-signal:

vo t a1vi t

Linear

Sinusoidal waveform

Zs
vi(t)

Vs

ZL

vo(t)

Small-Signal Amplifier (SSA)

All amplifiers are inherently nonlinear.

However when the input signal is small, the input and output
relationship of the amplifier is approximately linear.
vo t a1vi t a2vi 2 t a3vi3 t H .O.T . a1vi t

When vi(t)0 (< 2.6mV)

vo t a1vi t

Linear relation

(1.1)

This linear relationship applies also to current and power.

An amplifier that fulfills these conditions: (1) small-signal operation (2)
linear, is called Small-Signal Amplifier (SSA). SSA will be our focus.
If a SSA amplifier contains BJT and FET, these components can be
replaced by their respective small-signal model, for instance the
hybrid-Pi model for BJT.
6

Example 1.1 - An RF Amplifier Schematic (1)

DC supply

Zs

Input
Matching
Network

Amplifier

Output
Matching
Network

Vs

ZL
RF power flow

Typical RF Amplifier Characteristics

To determine the performance of an amplifier, the following

characteristics are typically observed.
1. Power Gain.
2. Bandwidth (operating frequency range).
Important to small-signal
3. Noise Figure.
amplifier
4. Phase response.
5. Gain compression.
6. Dynamic range.
Important parameters of
large-signal amplifier
7. Harmonic distortion.
(Related to Linearity)
8. Intermodulation distortion.
9. Third order intercept point (TOI).

Power Gain

For amplifiers functioning at RF and microwave frequencies, usually

of interest is the input and output power relation.
The ratio of output power over input power is called the Power Gain
(G), usually expressed in dB.
Power Gain

Output Power
G 10 log10
dB
Input
Power

(1.2)

There are a number of definition for power gain as we will see shortly.
Furthermore G is a function of frequency and the input signal level.

Why Power Gain for RF and Microwave

Circuits? (1)

Power gain is preferred for high frequency amplifiers as the

impedance encountered is usually low (due to presence of parasitic
capacitance).
Power = Voltage x Current

For instance if the amplifier is required to drive 50 load the voltage

across the load may be small, although the corresponding current
may be large (there is current gain).
For amplifiers functioning at lower frequency (such as IF frequency), it
is the voltage gain that is of interest, since impedance encountered is
usually higher (less parasitic).
For instance if the output of IF amplifier drives the demodulator
circuits, which are usually digital systems, the impedance looking into
the digital system is high and large voltage can developed across it.
Thus working with voltage gain is more convenient.
10

Why Power Gain for RF and Microwave

Circuits? (2)

Instead on focusing on voltage or current gain, RF engineers focus on

power gain.
By working with power gain, the RF designer is free from the
constraint of system impedance. For instance in the simple receiver
block diagram below, each block contribute some power gain. A large
voltage signal can be obtained from the output of the final block by
attaching a high impedance load to its output.

RF signal
power
1 W

15 W

75 W

BPF

v(t)

IF signal
power

4.90 V

7.5 mW

BPF

LNA

IF Amp.
400

RF Portion
(900 MHz)

LO

IF Portion
(45 MHz)

2
V
Paverage
2R
11

Harmonic Distortion (1)

When the input driving signal is
small, the amplifier is linear.
Harmonic components are
almost non-existent.
Zs

Vs

ZL
f1

f1

2f1

3f1 4f1

Harmonics generation reduces the gain

of the amplifier, as some of the output
power at the fundamental frequency is
shifted to higher harmonics. This result in
gain compression seen earlier!

Pout

harmonics
Small-signal
operation
region
Pin

12

Harmonic Distortion (2)

When the input driving signal is
too large, the amplifier becomes
nonlinear. Harmonics are
introduced at the output.
Zs

Vs

ZL
f1

f1

2f1

3f1 4f1

Harmonics generation reduces the gain

of the amplifier, as some of the output
power at the fundamental frequency is
shifted to higher harmonics. This result in
gain compression seen earlier!

Pout

harmonics

Pin

13

Power Gain, Dynamic Range and Gain

Compression
Pout
(dBm)

Input and output at same frequency

Pin

Pout

Ideal amplifier

Gain compression
occurs here

30

Device
Burn
out

1dB

20
10

Saturation

Linear Region

0
-10
-20

Nonlinear
Region

Dynamic range (DR)

-30

Power gain Gp =
Pout(dBm) - Pin(dBm)
= -30-(-43) = 13dB

-40

1dB compression
Point (Pin_1dB)

-50

Noise Floor

-60
-70

-60

-50

-40

-30

-20

-10

10

Pin
20 (dBm)
14

Bandwidth

Power gain G versus frequency for small-signal amplifier.

Po dBm

Pi dBm

G/dB

Po dBm

3 dB

Pi dBm

Bandwidth
0

f / Hz
15

Intermodulation Distortion (IMD)

vo t a1vi t a2vi t a3vi t H .O.T .
2

|Vi|

ignored

vo t

vi t
f1 f2

Operating bandwidth
of the amplifier

|Vo|
IMD

Two signals v1, v2 with similar

amplitude, frequencies f1 and f2 f1-f2
near each other
2f1-f2

f1 f2

Usually specified
in dB

2f1
f1+f2

2f2-f1

3f1
2f2

2f1+f2

3f2

2f2+f1

These are unwanted components, caused by

the term 3vi3(t), which falls in the operating
bandwidth of the amplifier.
16

Noise Figure (F)

The amplifier also introduces noise into the output in
addition to the noise from the environment.
Assuming small-signal operation.
Smaller SNRin

Zs

Vs
SNR:
Signal to Noise
Ratio

Noise Figure (F)= SNRin/SNRout

Since SNRin is always larger
than SNRout, F > 1 for an
amplifier which contribute noise.

ZL

Larger SNRout

17

Power Components in an Amplifier

Zs

Amplifier

Vs

ZL
2 basic sourceload networks

Approximate
Linear circuit
Zs

Z2

PAs

Z1

Vs
Pin
PRs

VAmp

PAo

PL
ZL

PRo
18

Power Gain Definition

From the power components, 3 types of power gain can be defined.

Power Gain G p

Power delivered to load PL

Input power to Amp.

Pin

Available Power Gain G A

Available load Power PAo

Available Input power PAs

PL
Power delivered to load
Transducer Gain GT

Available Input power PAs

(2.1a)
(2.1b)
(2.1c)

The effective power gain

GP, GA and GT can be expressed as the S-parameters of the amplifier

and the reflection coefficients of the source and load networks. Refer
to Appendix 1 for the derivation.
19

Naming Convention
Zs

Amplifier

Vs

ZL

s
2 - port
Network

Source
Network

s11
s
21
1

In the spirit of highfrequency circuit design,

where frequency response
of amplifier is characterized
by S-parameters and
reflection coefficient is
used extensively
instead of impedance,
power gain can be expressed
in terms of these parameters.

L
Load
Network

s12
s22
2

20

TWO-PORT POWER GAIN

Figure 7.1: A two port network with general source and load impedance.

21

Power Gain Definition

From the power components, 3 types of power gain can be defined.

Power Gain G p

Power delivered to load PL

Input power to Amp.

Pin

Available Power Gain G A

Available load Power PAo

Available Input power PAs

PL
Power delivered to load
Transducer Gain GT

Available Input power PAs

(2.1a)
(2.1b)
(2.1c)

The effective power gain

GP, GA and GT can be expressed as the S-parameters of the amplifier

and the reflection coefficients of the source and load networks. Refer
to Appendix 1 for the derivation.
22

TWO-PORT POWER GAIN

Power Gain = G = PL / Pin is the ratio of power dissipated in the load ZL to
the power delivered to the input of the two-port network. This gain is
independent of Zs although some active circuits are strongly dependent on
ZS.
Available Gain = GA = Pavn / Pavs is the ratio of the power available from
the two-port network to the power available from the source. This assumes
conjugate matching in both the source and the load, and depends on ZS but
not ZL.
Transducer Power Gain = GT = PL / Pavs is the ratio of the power delivered
to the load to the power available from the source. This depends on both ZS
and ZL.
If the input and output are both conjugately matched to the two-port, then
the gain is maximized and G = GA = GT
23

TWO-PORT POWER GAIN

From the definition of S parameters:

V1 S11V1 S12V2 S11V1 S12LV2

[7.1a]

V2 S 21V1 S 22V2 S 21V1 S 22LV2

[7.1b]

Eliminating V2- from [7.1a]:

Z Z0
V1
S S
in S11 12 21 L in
V1
1 S 22L Z in Z 0

[7.2]

S S
Z Z0
V2
S 22 12 21 S out
V2
1 S11S Z out Z 0

[7.3]

out

24

TWO-PORT POWER GAIN

By voltage division:

Z in
V1 VS
V1 V1 V1 1 in
Z S Z in
Using:

Solving for V1+:

1 in
Z in Z 0
1 in
VS 1 S
V
2 1 S in

[7.4]

[7.5]

[7.6]

25

TWO-PORT POWER GAIN

The average power delivered to the network:

1
Pin
V1 1 in
2Z 0

8Z
VS

1 S

1 S in

1
2

in

[7.7]

The power delivered to the load is:

PL
PL

2
1

2Z 0
VS

2
2

2Z 0

1
1

S 21

1 S 22 L
S 21

[7.8]

L
2

1 1
2

L
2

[7.9]
2

8Z 0 1 S 22 L 1 S in

2
26

TWO-PORT POWER GAIN

The power gain can be expressed as:

S 21 1 L
PL
G

Pin 1 in 2 1 S 22 L
2

[7.10]

The available power from the source:

Pavs Pin

in S

1 S

8Z 0 1 S

Vs

The available power from the network:

Pavn PL

L out

Vs

S 21 1 out 1 S
2

8Z 0 1 S 1
22 out
S in

[7.11]

[7.12]

L out

27

TWO-PORT POWER GAIN

The power available from the network:

Pavn

Vs

S 21 1 S

8Z 0 1 S11S 1 out
2

The available power gain:

S 21 1 S
2

The transducer power gain:

[7.13]

P
G A avn
Pavs 1 out 2 1 S11S

[7.14]

S 21 1 S 1 L
PL
GT

2
2
Pavs
1 S 22 L 1 S in
2

[7.15]

28

Summary of Important Power Gain Expressions

and the Gain Dependency Diagram
s

1 s
11

(2.2a)

22

s
1 s
22

2
11

s21 1 L

GP
2
2
1 s22L 1 1

(2.2b)

11

2
s11 s12
s

21 s22

1 2 s 2 1 2
L
21
s

GT
2
2
1 s22L 1 1s

s s s s

GT

GA

1 2 s 2
s
21

GA
2
2
1 s11s 1 2

22

12

(2.2c)

(2.2d)

(2.2e)
21

Note:
All GT, GP, GA, 1 and 2
depends on the Sparameters.
The Gain Dependency Diagram

GP

29

TWO-PORT POWER GAIN

A special case of the transducer power gain occurs when both input and
output are matched for zero reflection (in contrast to conjugate
matching).

GT S 21

[7.16]

Another special case is the unilateral transducer power gain, GTU where
S12=0 (or is negligibly small). This nonreciprocal characteristic is
common to many practical amplifier circuits. in = S11 when S12 = 0, so
the unilateral transducer gain is:

GTU

S 21 1 S
2

1
2

1 S11S 1 S 22in
2

[7.17]

30

TWO-PORT POWER GAIN

Figure 7.2: The general transistor amplifier circuit.

31

TWO-PORT POWER GAIN

The separate effective gain factors:

GS

1 S

1 in S

G0 S 21
GL

2
2

[7.18a]

1 L

[7.18b]
2

1 S 22 L

[7.18c]

32

TWO-PORT POWER GAIN

If the transistor is unilateral, the unilateral transducer gain reduces
to GTU = GSG0GL , where:

GS

1 S

1 S11S

G0 S 21
GL

2
2

[7.19a]

1 L

[7.19b]
2

1 S 22 L

[7.19c]

33

Example 1 Familiarization with the Gain

Expressions

An RF amplifier has the following S-parameters at fo: s11=0.3<-70o,

s21=3.5<85o, s12=0.2<-10o, s22=0.4<-45o. The system is shown
below. Assuming reference impedance (used for measuring the Sparameters) Zo=50, find:
(a) GT, GA, GP.
(b) PL, PA, Pinc.
40
Amplifier
5<0o

s11 s12
s

21 s22

ZL=73

34

Example 1 Cont...

Step 1 - Find s and L .

Step 2 - Find 1 and 2 .
Step 3 - Find GT, GA, GP.
Step 4 - Find PL, PA.

Z Z

s11 DL
1 s22L

PA

Try to derive
These 2 relations

Pin PA 1

Z1 Z s
Zo
Z1 Z s

0.0714W

PL GP Pin 0.9814W

Again note that this is an

analysis problem.

L Z L Z o 0.187
L
o

0.146 j 0.151

s Ds
2 22
0.265 j 0.358
1 s11s

1 13.742
G
1 s 1
s

Vs
0.078W
8ReZ s

Z Z

s Z s Zo 0.111
s
o

21

22

GA

1
s

s21

2
2

14.739

1 s11s 1 2

1 2 s 2 1 2
L
21
s

12.562
GT
2
2
1 s22L 1 1s
35

STABILITY
In the circuit of Figure 7.2, oscillation is possible if either the input or
output port impedance has the negative real part; this would imply that
|in|>1 or |out|>1.

in and out depends on the source and load matching networks, the stability
of the amplifier depends on S and L as presented by matching networks.
Unconditionally stable: The network is unconditionally stable if |in| < 1
and |out| < 1 for all passive source and load impedance (ex; |S| < 1 and
|| < 1).
Conditionally stable: The network is conditionally stable if |in| < 1 and
|out| < 1 only for a certain range of passive source and load impedance.
This case also referred as potentially unstable.
The stability condition of an amplifier circuit is usually frequency
dependent.
36

STABILITY CIRCLES
The condition that must be satisfied by S and L if the amplifier is
to be unconditionally stable:

S12 S 21L
in S11
1
1 S 22L

[7.20a]

S S
S
1
1 S

[7.20b]

12

out

21

22

11

The determinant of the scattering matrix:

S11S 22 S12 S 21

[7.21]

37

STABILITY CIRCLES
The output stability circles:

CL

CS

S 22

RL

The input stability circles:

22

11
2

S12 S 21
S 22
2

RS

11

22
2

S12 S 21
S11
2

[7.22b]

S11
2

[7.22a]

[7.23a]

[7.23b]

38

STABILITY CIRCLES

Figure 7.3: Output stability circles for conditionally stable device.

(a) |S11| < 1 (b) |S11| > 1

39

STABILITY CIRCLES
If the device is unconditionally stable, the stability circles must be
completely outside (or totally enclose) the Smith chart.

CL RL 1 S11 1

[7.24a]

CS RS 1 S 22 1

[7.24b]

40

STABILITY TEST
Rollets condition:

1 S11 S 22
2

K
the auxiliary condition:

the test:

[7.25]

S11S22 S12 S21 1

[7.26]

2 S12 S 21

1 S11

11

S 22 S S12 S 21

[7.27]

41

Example 2
The S parameters for the HP HFET-102 GaAs FET at 2 GHz with a
bias voltage of Vgs = 0 are given as follow (Z0 = 50 Ohm):
S11 = 0.894 < -60.6
S21 = 3.122 < 123.6
S12 = 0.020 < 62.4
S22 = 0.781 < -27.6
Determine the stability of this transistor using the K- test and the
test, and plot the stability circles on the Smith Chart

42

Example 2
Remember, criteria for unconditional stability is:

For the K- test:

S S S S 1
11

22

12

1 S11 S 22
2

21

2 S12 S 21

For the test:

1 S11

11

S 22 S S12 S 21

43

Example 2
Calculation results:

For the K- test:

S S S S 0.696 1
11

22

12

1 S

11

21

22

2S S
12

For the test:

1 S

0.607 1

21

0.86 1

11

S S S S

22

11

12

21

Which indicates potential instability

44

Example 2
Calculation for the input and output stability circles:
Output stability circle center and radius:

S
1.361 47
S

22

11

22

S S
R
0.50
S
12

21

22

Input stability circle and radius

C
S

S
1.132 68
S

11

22

11

S S
R
0.199
S
12

11

21

45

STABILITY

Figure 7.4: Example of stability circles

46

SINGLE STAGE TRANSISTOR

AMPLIFIER DESIGN
Maximum power transfer from the input matching network to the
transistor and the maximum power transfer from the transistor to the
output matching network will occur when:

in

[7.28a]

out

[7.28b]

Then, assuming lossless matching sections, these conditions will

maximize the overall transducer gain:

GTm ax

1
1 S

S 21

1 L

1 S 22 L

[7.29]
2

47

SINGLE STAGE TRANSISTOR

AMPLIFIER DESIGN
In the general case with a bilateral transistor, in is affected by out,
and vice versa, so that the input and output sections must be matched
simultaneously.

S12 S 21L
S11
1 S 22 L

S 22

S12 S 21S

1 S11S

[7.30a]

[7.30b]

48

SINGLE STAGE TRANSISTOR

AMPLIFIER DESIGN
The solution is:

B B 4C

[7.31a]

2C

B B 4C

2C

[7.31b]

49

SINGLE STAGE TRANSISTOR

AMPLIFIER DESIGN
The variables are defined as:

B1 1 S11 S 22

B2 1 S 22 S11

C1 S11 S

[7.32a]

[7.32b]

22

[7.32c]

11

[7.32d]

C2 S 22 S

50

SINGLE STAGE TRANSISTOR

AMPLIFIER DESIGN
When S12 = 0, it shows that S = S11* and L = S22*, and the maximum
transducer gain for unilateral case:

GTU max

1
1 S11

S 21

[7.33]

1 S22

When the transistor is unconditionally stable, K > 1, and the max

transducer power gain can be simply re-written as:

GTmax

S 21
S12

The maximum stable gain with K = 1:

Gmsg

K 2 1

[7.34]

[7.35]

S 21
S12

51

Example 3
Design an amplifier for a maximum gain at 4.0 GHz. Calculate the
overall transducer gain, G, and the maximum overall transducer gain
GTMAX. The S parameters for the GaAs FET at 4 GHz given as follow
(Z0 = 50 Ohm):
S11 = 0.72 < -116
S21 = 2.60 < 76
S12 = 0.03 < 57
S22 = 0.73 < -68

52

Example 3 (Cont)
Determine the stability of this transistor using the K- test

S S S S 0.488 162
11

22

1 S

12

2
11

21

2
22

2S S
12

1.195

21

Since || < 1 and K > 1, the transistor is unconditionally stable at 4.0

GHz.

53

Example 3 (cont)
For the maximum gain, we should design the matching sections for a
conjugate match to the transistor. Thus, S = in* and L = out*, S
and L can be determined from;

B B 4C

0.872 123

2C

B B 4C

2C

0.876 61

54

Example 3
The effective gain factors can calculated as:

G
S

1
1 S

G S
0

G
L

2
21

4.17 6.20 dB

2
11

6.76 8.30dB

1 S
22

1.67 2.22dB

So the overall maximum transducer gain will be;

G m ax 6.20 8.30 2.22 16 .7dB

T

55

UNILATERAL FOM
In many practical cases |S12| is small enough to be ignored, the device
then can be assumed to be unilateral, which greatly simplifies design
procedure
Error in the transducer gain caused by approximating |S12| as zero is
given by the ratio GT/GTU, and be bounded by:

1
G
1

(1 U ) G
(1 U )
T

TU

Where U is defined as the unilateral figure of merit

S S S S
12

21

11

22

(1 S )(1 S )
2

11

22

56

Example 4
An FET is biased for minimum noise figure, and has the following S
parameters at 4 GHz:
S11 = 0.60 < -60
S21 = 1.90 < 81
S12 = 0.05 < 26
S22 = 0.50 < -60
For design purposes, assume the device is unilateral and calculate the
max error in GT resulting from this assumption.

57

Example 4 (cont)
To compute the unilateral figure of merit;

S S S S
12

21

11

22

(1 S )(1 S )
2

11

0.059

22

Then the ratio of GT/GTU is bounded as;

1
G
1

(1 U ) G
(1 U )
T

TU

G
0.891
1.130
G
T

TU

58

Example 4 (cont)
In dB, this is;

0.50 G G 0.53 dB
T

TU

Where GT and GTU are now in dB. Thus we should expect less than
about 0.5 dB error in gain.

59

CONSTANT GAIN CIRCLES

In many cases it is desirable to design for less than the max obtainable
gain, to improve bandwidth or to obtain a specific value for an
amplifier gain.
Mismatches are purposely introduced to reduce the overall gain
Procedure is facilitated by plotting constant gain circles on the Smith
Chart
Represents loci of S and L, that give fixed values of GS and GL.
To simplify the discussion, we will only treat the case of a unilateral
device

60

CONSTANT GAIN CIRCLES

The expression for the GS and GL for the unilateral case is given by:

G
S

1 S
11

1 S
22

These gains are maximized when S = S11* and L = S22* :

G m ax
S

1 S

2
11

1
G m ax
1 S

22

61

CONSTANT GAIN CIRCLES

Now we define normalized gain factors gS and gL as;

1
G
g

(1 S )
G max 1 S
2

11

11

1
G
g

(1 S )
G max 1 S
2

22

22

Thus we have a that: 0 gS 1, and 0 gL 1. A fixed value of gS and gL

represents circles in the S and L planes.

62

CONSTANT GAIN CIRCLES

Input constant gain circles:

CS
RS

g S S11

1 1 g S S11

[7.37a]

1 g S 1 S11

1 1 g S S11

[7.37b]

Output constant gain circles:

CL
RL

g L S 22

1 1 g L S 22

1 g L 1 S 22

1 1 g L S 22

[7.38a]

2
2

[7.38b]

63

Example 5
Design an amplifier to have a gain of 11 dB at 4 GHz. Plot constant
gain circles for GS = 2 dB and 3 dB; and GL = 0 dB and 1 dB. The
FET has the following S parameters (Z0 = 50 ):
S11 = 0.75 < -120
S21 = 2.50 < 80
S12 = 0.00 < 0
S22 = 0.60 < -85

64

Example 5 (cont)
Since S12 = 0 and |S11| < 1 and |S22| < 1, the transistor is unilateral and
unconditionally stable. We calculate the max matching section gains
as;

G m ax
S

G m ax
L

1 S

2.29 3.6dB

11

1 S

1.56 1.9dB

22

The gain of the mismatched transistor is;

G S
0

2
21

6.25 8.0dB
65

Example 5 (cont)
So the max unilateral transducer gain is

G U m ax 3.6 1.9 8.0 13 .5dB

T

Thus we have 2.5 dB more available gain than required by specs,

since the design only requires 11 dB gain. However, the question also
asked us to analyze the effect of having:
Condition 1: GS = 3 dB and GL = 0 dB
Condition 2: GS = 2 dB and GL = 1 dB
(Note that these conditions must happens at the same time in order to
keep the gain at 11 dB.)
66

Example 5 (cont)
For condition 1 (input side), when GS = 3 dB:

G
g
0.875
G m ax
S

gS
C
1 1 g S
S

R
S

11

1 g 1 S
S

0.706 120

11

1 1 g S
S

2
11
2

0.166

11

67

Example 5 (cont)
For condition 1 (output side), when GL = 0 dB:

G
g
0.640
G m ax
L

gS
C
1 1 g S
L

R
L

22

1 g 1 S
L

0.440 70

22

1 1 g S
L

2
22
2

0.440

22

68

Example 5 (cont)

69

LOW NOISE AMPLIFIER DESIGN

In receiver applications especially, it is often required to have a
preamplifier with as low a noise figure as possible since, the first
stage of a receiver front end has the dominant effect on the noise
performance of the overall system.
Generally it is not possible to obtain both minimum noise figure and
maximum gain for an amplifier, so some sort of compromise must
be made. This can be done by using constant gain circles and circles
of constant noise figure to select a usable trade of between noise
figure and gain.

RN
F Fm in
YS Yopt
GS

[7.39]

70

LOW NOISE AMPLIFIER DESIGN

For a fixed noise figure, F, the noise figure parameter, N, is given as:

F Fm in
N
1 opt
4 RN Z 0

[7.40]

The circles of constant noise figure:

CF
RF

opt

[7.41a]

N 1

N N 1 opt

[7.41b]

N 1
71

Example 6
An GaAs FET amplifier is biased for minimum noise figure and has
the following S-parameters (Z0 = 50 ):

S11 = 0.75 < -120

S21 = 2.50 < 80
S12 = 0.00 < 0
S22 = 0.60 < -85
opt = 0.62 < 100
Fmin = 1.6 dB
RN = 20
For design purposes, assume the unilateral. Then design an amplifier
having 2.0 dB noise figure with the max gain that is compatible with
this noise figure.
72

Example 6 (cont)
Next use the formulas to compute the center and radius of the 2 dB
noise figure circle:

F F
N
1
4R Z

min

opt

0.0986

C
0.56 100
N 1
opt

R
F

N N 1

opt

N 1

0.24

The gain of the mismatched transistor is

73

Example 6 (cont)
The noise figure circle is plotted in the figure. Min noise figure (Fmin
= 1.6 dB) occurs for S = opt = 0.62<100o
GS (dB)

gS

CS

RS

1.0

0.805

0.52<60o

0.300

1.5

0.904

0.56<60o

0.205

1.7

0.946

0.58<60o

0.150

It can be seen that GS = 1.7 dB gain circle just intersects the F = 2.0
dB noise figure circle, and any higher gain will result in a worse
noise figure.

74

Example 6 (cont)
For the output section we choose L = S22* = 0.5<60o for a max GL
of:

1
G
1 S

G S
0

1.33 1.25 dB

22

3.61 5.58dB

2
21

G U m ax G G G 8.53 dB
T

75

Example 6 (cont)

76