Vit Ting Anh Hc Thut

T chc lp vit bo khoa hc K thut ng trn tp

ch quc t (17)
(Electrical Engineering, Industrial Engineering)
Kha Thi c
i hc Y Dc TP H Ch Minh Gim c trung tm vit bo khoa hc bng ting
Anh

http://www.chineseowl.idv.tw

Tiu s c nhn
Kha Thi c (Ted Knoy) dy vit ting Anh k
thut trong cc trng i hc i Loan hn hai
mi nm. ng l tc gi ca mi bn cun sch
v vit ting Anh k thut v chuyn nghip. ng
thnh lp mt trung tm vit ting Anh ti trng i
hc Y Yunpei ng thi cng l ging vin ton thi
gian ti trng. ng chnh sa trn 55,000 bi
vit cho vic ng bo nghin cu khoa hc t nm
1989. ng l cng nh bin tp ting anh cho mt s
tp ch v khoa hc, k thut v y hc ca i Loan.

A. Nn tng (Background)

Thit lp cc xut nghin cu (Setting of research proposal): M

t mt xu hng ph bin, pht trin hoc hin tng trong lnh vc ca
bn ngi c c th hiu c bi cnh m bn xut nghin cu
ang c thc hin .

Vn nghin cu (Research problem) : M t cc hn ch chnh hoc

tht bi ca cc nghin cu trc y hoc cc phng php nghin
cu khi gii quyt cc xu hng, pht trin hoc hin tng nu .

c im k thut nh lng ca vn nghin cu (Quantitative

specification of research problem): nh lng hoc a ra mt v d
v vn nghin cu c trch dn trong ti liu tham kho trc .

Tm quan trng ca vn nghin cu (Importance of research

problem) : M t cc hu qu v mt l thuyt v thc t nu khng gii
quyt vn nghin cu.

B. Thc hin (Action)

Mc tiu nghin cu (Research objective) : M t mc tiu ca nghin

cu xut ca bn v bao gm cc c im chnh ring bit ca
nghin cu t c mc tiu nghin cu , iu m khng c
thc hin trong nghin cu trc y ( mt cu )

Phng php t c mc tiu nghin cu (Methodology to

achieve research objective) : M t ba hoc bn bc chnh t
c mc tiu nghin cu ca bn .

Kt qu d kin ( Anticipated results) : M t cc kt qu nh lng

m bn hy vng s t c trong nghin cu ca bn.

ng gp trong lnh vc l thuyt v thc tin (Theoretical and

practical contribution to field) : M t cch thc phng php hoc
kt qu nghin cu xut ca bn s ng gp v mt l thuyt trong
lnh vc nghin cu, quy lut v cng ng gp thit thc trong sn
xut, ngnh cng nghip dch v.

V d 1: Electrical Engineering
Thit lp cc xut nghin cu Logic circuits can
achieve optimization by full custom design flow, i.e. manual
design and layout, thus enhancing product performance
and lowering costs more than that achieved by the design
flow of hardware description language (HDL). Conversely,
a larger logic ASIC includes more than 1,000,000 gates in a
chip, which is difficult for full custom design to implement.
Vn nghin cu For a larger ASIC, full custom design
flow requires additional personnel, making it extremely
difficult to achieve time to market delivery.

V d 1 (cont.)
c im k thut nh lng ca vn nghin cu
For instance, HDL design flow requires half the production
time than full custom design does. Such a benefit is
proportional to the logic ASIC scale.
Tm quan trng ca vn nghin cu Owing to the
extensive time required for modification and verification,
adopting full custom design in different processes is difficult
to re-use as an IP, making it impossible to satisfy market
demand.

V d 1 (cont.)
Mc tiu nghin cu Based on the above, we should develop a
HDL-based scheme for designing logic circuits, capable not only of
re-use as an IP in different processes, but also of automatic
regeneration of physical circuits.
Phng php t c mc tiu nghin cu To do so, all
logic circuits can be described by program editing. The programs
can then be synthesized to gate level formats. Next, all gates can
be placed and routed by auto-place-and-route (APR) software to
physical layered circuits. Additionally, simulation parameters can be
estimated from APR software. Moreover, the APR results can be
confirmed via simulation that includes the processed parameters.
Furthermore, all description programs can be re-used.

V d 1 (cont.)
Kt qu d kin In addition to automatically
generating production via software, the proposed
HDL-based scheme can decrease personnel by 50%
for the same IP procedure and accelerate market to
time delivery.
ng gp trong lnh vc l thuyt v thc tin
Automatic design flow of the proposed scheme can
avoid manually controlled errors, ultimately
increasing product throughput and reducing
personnel.

V d 2: Electrical Engineering
Thit lp cc xut nghin cu Device mis-matching always
complicates circuitry design owing to the inability to identify the
origin, thus accentuating the importance of process control.
Vn nghin cu In practice, circuit designers must add an
increasing number of devices in the circuitry to overcome process
deviation. For instance, mis-matching can generate a yield loss
of 20-30%.
c im k thut nh lng ca vn nghin cu
Whereas a larger chip size implies a higher product price, a
higher retail price lowers market competitiveness.
Tm quan trng ca vn nghin cu Therefore, the
inability to resolve this mis-matching dilemma makes it impossible
to detect and control process variation in wafer processing.

V d 2 (cont.)
Mc tiu nghin cu Based on the above, we should investigate the
correlation between process parameters and product yield.
Phng php t c mc tiu nghin cu To do so, by adopting
the statistical process control (SPC) method, process parameters can be
collected from the in-line WIP. Major process-related factors can then be
identified using correlation analysis. Next, the product yield can be verified
based on these factors. Additionally, these process parameters can be
stringently controlled to decrease the loss of product yield.
Kt qu d kin As anticipated, while analysis results can clarify the
correlation between process parameters and product yield, circuitry
designers can focus on incorporating the above factors without increasing
device size,
ng gp trong lnh vc l thuyt v thc tin ultimately reducing the
chip area and lowering the retail price.

V d 3: Electrical Engineering
Thit lp cc xut nghin cu As an integral part of the current mode dc
to dc system, the current sensing block influences the stability of a close loop
and contributes to the non-linearity of output voltage significantly.
Vn nghin cu However, the conventionally adopted current sensing
block varies with process, temperature and power supply at a range of 1030%.
c im k thut nh lng ca vn nghin cu The inability to
adequately control the current sensing block might lead to instability of the dc to
dc system and adversely impact the unity of a chip, leading to testing errors.
Tm quan trng ca vn nghin cu Identifying an acceptable current
sensing value increasing the testing time and lowers the product yield,
subsequently delaying delivery to market and lowering market competitiveness.

V d 3 (cont.)
Mc tiu nghin cu Based on the above, we should design
a sensing circuit that can ensure proportionality of the current
flowing through power mos, but also can be modified according
to the voltage value of the current.
Phng php t c mc tiu nghin cu To do so,
a high speed and easily implemented sensing circuit can be
analyzed under various loading currents and linear variations
with the loading current. The sensing value can then be only
slightly altered less than during simulation with various
temperatures. Next, the value of variation in the sensing circuit
can be considered acceptable during simulation with various
process models.

V d 3 (cont.)
Kt qu d kin As anticipated, given various process
models and temperatures, the value of variation in the
proposed sensing circuit is lower than 1%. Additionally, the
sensing value is linear with the loading current.
ng gp trong lnh vc l thuyt v thc tin
Importantly, the proposed sensing circuit can facilitate the
precise measurement of the current in various sizes of power
mos. Moreover, the sensing circuit can be embedded in a
chip without the need for an outer resistor, as required by the
conventional method. Such features can ensure that its
reliable application complies with consumer specifications.

V d 4: Industrial Engineering
Thit lp cc xut nghin cu Process variation
has significantly abated loss of product yield.
Vn nghin cu However, given the instability
and inaccuracy of production equipment, fabs are
especially problematic in process control.
c im k thut nh lng ca vn nghin
cu Given the constant role of process variation in
manufacturing, a small percentage of product yield
loss occurs in manufacturing ICs,
Tm quan trng ca vn nghin cu ultimately
increasing the retail costs of IC products.

V d 4 (cont.)
Mc tiu nghin cu Based on the above, we should develop an analysis
method to clarify the variation of process parameters and product yield rate are
related, e.g., resistors, using various resistor widths on a circuit layout.
Phng php t c mc tiu nghin cu To do so, product yield rate
can be analyzed by placing the product with various resistor widths on different
wafers that are to be manufactured in a fab. The yield rate of these wafers can
then be monitored, with the optimal resistor width obtained when the wafer yield
rate is the highest.
Kt qu d kin As anticipated, the proposed analysis method can enable the
optimal resistor width to reduce the influence on product yield rate when the
resistors vary, thus increasing product yield rate.
ng gp trong lnh vc l thuyt v thc tin By varying the process
parameters, the proposed method can analyze the variation in product yield rate,
thus decreasing the overhead manufacturing costs and increasing market
competitiveness.

Ti liu tham kho

Knoy, T (2002) Writing Effective Work
Proposals. Taipei: Yang Chih Publishing

Further details can be found at

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