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CDAC,Mohali
Agenda
MCS-51 family architecture
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Computer Organization
Control unit
ALU
Memory
Output
Input
Register
Processor
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Contd
32 bi-directional and individually addressable I/O lines.
Which form four 8-bit I/O Ports (P0-P3).
Two 16-bit timer/counters
Full duplex UART
6 interrupt sources with two priority levels
On-chip clock oscillator
210 bit-addressable locations.
Oscillator & Clock Circuit
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8051
8052
ROM
0K
4K
8K
RAM
128B
128B
256B
Timers
I/O pins
32
32
32
Serial p.
Interrupt
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Logic Symbols
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ALTERNATE USE
SFR
P3.0 RXD
SBUF
P3.1 TXD
SBUF
P3.2 INT0
External Interrupt 0
TCON.1
P3.3 INT1
External Interrupt 1
TCON.3
P3.4 T0
TMOD
P3.5 T1
TMOD
P3.6 WR
P3.7 RD
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Pulse P: It
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CPU Timing
Each state is divided into 2 phases, phase-1 and phase-2.
P1
P2
State 1
State 2
State 3
State4
State 5
State 6
ALE
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Flags and PSW : Flags are grouped inside PSW and PCON
registers.In 8051 there are 7 flags, 4 math flags which
respond automatically to the outcomes of the math
operations and 3 general purpose flags which can be set or
reset by the programmer.
Math flags are - Auxiliary carry(AC), Carry(C), Parity(P)
and Overflow (OV)
General Purpose Flags - FO, GF0 and GF1
PSW :
CY
AC
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F0
RS1
RS2
OV
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Symbol
Function
CY
AC
F0
User flag 0
RS1
RS0
OV
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