Interrupts in 8085

Interrupt
Interrupt is a process where an
external device can seek the
attention of the microprocessor.
Interrupt is INPUT towards the
processor
The process is asynchronous.

Classifications
Interrupt
Hardware
Software
Vectored/Non Vectored
Maskable

Available Pins for Interrupt in 8085

chip

Maskable Interrupts
TRAP is Non-Maskable Vectored
Interrupt
RST 7.5, 6.5, 5.5 Maskable Vectored
Interrupt
Masking can be done using EI(Enable
Interrupt) and SIM (Set Interrupt
Mask) Instructions

Set Interrupt Mask (SIM)

Managing Vectored
Interrupts
Assume RST 7.5 and RST 6.5
interrupts are enabled in a 8085
system. The job of the processor is to
provide service to interrupt with
highest priority.

Program Structure without

Attending Pending Interrupt
Main Program
8500H LXI SP, Stack
add
MVI A, 09H
SIM
EI
.
.
.

Monitor Program
003CH JMP A100H
Interrupt Service
Routine
A100H DI
.
.
EI
RET

Pending Interrupts
Due to presence of several input
lines other interrupt request may
occur while one interrupt is being
served. This is known as Pending
Interrupt.

Read Interrupt Mask

D4,D5,D6 are 1 for pending

Interrupts

Program Structure Considering

Pending Interrupt
Main Program
8500H LXI SP, Stack
add
MVI A, 09H
SIM
EI
.
.
.

Monitor Program
003CH JMP XX05H
Interrupt Service Routine
XX05H DI
.
.
RIM
ANI 20H
JNZ L1
EI
RET
L1:
.
.
SIM
JMP Serivce

Software Interrupts
8 software interrupts i.e Restart
instructions (RST0 RST7)
----For each interrupt a
Subroutine is executed at pre
defined location.

Non Vectored Interrupt

Non Vectored Interrupt

When the power is ON for the first time,
RESETIN(bar) signal goes low
it resets the 8085
resets the INTE (S-R) F/F
the entire interrupt structure is disabled.
(Reset in (bar) signal is followed by an NOT gate
before entering S-R flip flop)

When INTE F/F is reset, except for TRAP no

other interrupt signal can interrupt the
process.

INTR Process
Main stack program initializes stack pointer
Process can be interrupted using a switch
Processor checks INTR 1 clock period before
the last T state
Microprocessor completes the current
execution, disables interrupt, sends out
INTA(bar)
INTA(bar) using hardware circuitry can
access any RST instruction as per design

INTR Process Continued

Program is transferred to specific
memory location (i.e at 0018 for RST
3)
The location should have JUMP
instruction to transfer the program to
Interrupt Service Routine
Service routine enables interrupt
before returning to main program