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    sumit
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    This document discusses superscalar processors, which can execute multiple instructions per clock cycle by exploiting instruction-level parallelism. A superscalar processor fetches and decodes multiple instructions simultaneously and executes them in parallel whenever possible. It handles dependencies between instructions through techniques like branch prediction and register renaming to maintain an uninterrupted instruction stream. This allows for faster throughput than sequential execution at the same clock rate. All modern CPUs since 1998 are superscalar to achieve performance gains over scalar processors.

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    SUPERSCALAR_ARCHITECTURE.ppt

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    This document discusses superscalar processors, which can execute multiple instructions per clock cycle by exploiting instruction-level parallelism. A superscalar processor fetches and decodes multiple instructions simultaneously and executes them in parallel whenever possible. It handles dependencies between instructions through techniques like branch prediction and register renaming to maintain an uninterrupted instruction stream. This allows for faster throughput than sequential execution at the same clock rate. All modern CPUs since 1998 are superscalar to achieve performance gains over scalar processors.

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    3 views9 pages

    Superscalar Architecture

    Uploaded by

    sumit
    This document discusses superscalar processors, which can execute multiple instructions per clock cycle by exploiting instruction-level parallelism. A superscalar processor fetches and decodes multiple instructions simultaneously and executes them in parallel whenever possible. It handles dependencies between instructions through techniques like branch prediction and register renaming to maintain an uninterrupted instruction stream. This allows for faster throughput than sequential execution at the same clock rate. All modern CPUs since 1998 are superscalar to achieve performance gains over scalar processors.

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    of 9

    Ahmed Faraz

    Fall 2008

    ELEC6200-001

    Definition and
    Characteristics
    Superscalar processing is the ability to initiate
    multiple instructions during the same clock
    cycle.
    A typical Superscalar processor fetches and
    decodes the incoming instruction stream
    several instructions at a time.
    Superscalar architecture exploit the potential
    of ILP(Instruction Level Parallelism).

    Fall 2008

    ELEC6200-001

    Fetching and dispatching two instructions per


    cycle

    Fall 2008

    ELEC6200-001

    Uninterrupted stream of
    instructions
    The outcomes of conditional branch

    instructions are usually predicted in advance


    to ensure uninterrupted stream of instructions
    Instructions are initiated for execution in
    parallel based on the availability of operand
    data, rather than their original program
    sequence. This is referred to as dynamic
    instruction scheduling.
    Upon completion instruction results are
    resequenced in the original order.
    Fall 2008

    ELEC6200-001

    Superscalar Execution Example

    - With Register Renaming for


    WAR and WAW dependencies.

    Fall 2008

    ELEC6200-001

    .
    Register Renaming
    Example

    WAR dependency exist between LD r7,(r3) and SUB r3, r12,r11


    instructions

    With Register Renaming, the first write to r3 maps to hw3,while the second w
    maps to hw20.This converts four instruction dependency chain into 2 two ins
    chains, which can then be executed in parallel if the processor allows out of
    execution.

    Fall 2008

    ELEC6200-001

    Hardware Organization of a
    superscalar processor

    Fall 2008

    ELEC6200-001

    CONCLUSION
    It thereby allows faster CPU throughput than would

    otherwise be possible at the same clock rate.


    All general-purpose CPUs developed since about
    1998 are superscalar.
    The major problem of executing multiple

    instructions in a scalar program is the handling of


    data dependencies. If data dependencies are not
    effectively handled, it is difficult to achieve an
    execution rate of more than one instruction per
    clock cycle.

    Fall 2008

    ELEC6200-001

    References
    THE MICRO ARCHITECTURE OF SUPERSCALAR PROCESSORS BY

    JAMES E. SMITH, MEMBER, IEEE, AND GURINDAR S. SOHI, SENIOR MEMBER, IEEE

    http://en.wikipedia.org/wiki/Superscalar
    http://www.seas.gwu.edu/~bhagiweb/cs211/lectures/superscalar.pd

    f
    LIMITATION OF SUPERSCALAR MICROPROCESSOR PERFORMANCE

    Fall 2008

    THANG TRAN ,ADVANCED MICRO DEVICES, INC. AUSTIN, TEXAS 78741 AND CHUAN-LIN WU,DEPARTMENT OF
    ELECTRICAL AND COMPUTER ENGINEERING

    ELEC6200-001

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