System Bank Queue

Monitoring
By Ahmed Adel, Mohamed Essam, Eslam Mahmoud.
Under supervision of Dr. Ahmed Shalaby.

Problem?

Top module

Block structure diagram

Counter

Wtime block

address

ROM

data

Wtime block(2)

Main Control Block

Control Synthesis using DC

State machine

State machine

Control sensor

Control sensor(2)

Test plan
1

Test the number of customers till the full queue while the entrance sensor is hit

Test the full flag when the queue is full

During the test the work of the entrance sensor for more than one cycle to ensure that it increments only once.

Try to add an extra customer to test the alarm signal

Test the number of customers till the empty queue while the exit sensor is hit

During the test, the waiting time was being tested for different cases

Test results

Test results(2)

Test results(3)