NCUEE

FPGA
:
: ,
2013/3/28

FPGA

NcuEE
You

can verify your designs at any time by configuring the FPGA devices on
board via the download cable or hardware programmer.

FPGA Architecture

NcuEE

(Configurable Logic Blocks,CLB)

/ (I/O Blocks,IOB)
(Programmable Interconnects,PI)

Configurable Logic Block(CLB)

NcuEE

Combinational logic generated in a look up table(LUT)

Any function of available inputs
Function Generator
LUT output feeds CLB output or D input of flip-flop
Combinational output
Registered output

About Look-Up Table

Combinational Logic is stored in 24x1 SRAM LUTs
Generates any function of its inputs

NcuEE

Typically 4 inputs(F,G) & 3 inputs(H)

I/O Block (IOB)

NcuEE

Input,output or bidirectional
Direct or registered(or latched input)
Tri-State output
Programmable slew rate
Programmable thresholds

Programmable Interconnects

NcuEE

CLB
1

10

11

12

13

14

15

16

17

18

19

20

Switch
Matrix

CLB

Switch
Matrix

CLB

CLB

Switch Matrix
General Purpose Interconnect

Altera Stratix Logic Element

NcuEE

FPGA Design Flow

NcuEE

1.

Design Entry
in Schematic , Verilog and/or
VHDL
2.

3.

Implementation
includes translation , Placement &
Routing and bitstream generation

Download
directly to the Xilinx hardware
device(s) with Slave serial mode

NcuEE
1.
FileProjectName

C:\documents and
setting\ncuee

10

NcuEE
2. FPGA

11

NcuEE
3. Graphic

12

NcuEE
4. Enter Symbol

C:\maxplus2\max2lib\prim

C:\maxplus2\max2lib\mf
C:\maxplus2\max2lib\mega_lpm
5.

and gate, or gate ,input, output

prim

13

NcuEE

AND

AND IN OUT PIN

14


5.a Save & Compile

NcuEE

FileProject Save & Compile

15

NcuEE
5.b Compile
Compile

Warning Error

16

NcuEE
6.
MAX+plus II
Waveform Editor

17

NcuEE
7.
a. Insert Node

b. List Pin

7.

Pin

18

NcuEE

8.

FileProject Save & Simulate

19

FPGA

NcuEE

1 FPGA
2
3
4 LED
5

NcuEE

LED
A1~A4 B1~B4 Cin
FPGA
V6

AB1
U7
AA2
Y5
AA5
W5
W6

Y6

AB6 Y4 V7 V8 W7 AA7 Y7

LED

NcuEE

LED(
LED )
AA18 Y18 Y19 W18 AA20 U17 Y20 AB22

Pin Assign (1/2)

NcuEE

Pin Assignment
MAX+plus IIFloorplan Editor
FPGA

Pin Assign (2/2)

NcuEE

Assign
A1
V6
,V6

[A1@V6(I/O)]

Compile

Download FPGA (1/2)

NcuEE

Download -Zepper (or IDSA1K)

COM Port
SetupPreferences

Download FPGA (2/2)

NcuEE

1
1. project
2. FPGA

FPGA LED

NcuEE

altera MAX+plusII 1-bit Half adder

Download FPGA

27

Half-adder

NcuEE

NcuEE