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Design Process VLSI Lecture

The document describes the design process flow, which includes design conception, entry through schematic or HDL capture, synthesis, functional simulation to check for design correctness, physical design including timing simulation to ensure timing is met, and chip configuration. Key steps are architectural decisions on number of sub-blocks and interconnects, schematic or HDL entry describing the design, synthesis to implement the design, and multiple simulations to verify functionality and timing.

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Mohammod Ahad Arian
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42 views5 pages

Design Process VLSI Lecture

The document describes the design process flow, which includes design conception, entry through schematic or HDL capture, synthesis, functional simulation to check for design correctness, physical design including timing simulation to ensure timing is met, and chip configuration. Key steps are architectural decisions on number of sub-blocks and interconnects, schematic or HDL entry describing the design, synthesis to implement the design, and multiple simulations to verify functionality and timing.

Uploaded by

Mohammod Ahad Arian
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Design Process

Salahuddin Ahmed
Design Flow
Design Conception

Design Entry
Schematic HDL
Capture Entry

Synthesis

Functional Simulation

No Design
Correct ?
Yes

Physical Design

Timing Simulation

No Timing
Met ?
Yes

Chip Configuration
Design Specification
Algorithm
to be implemented with
mathematical representation
Number of IOs and number of bits in
each IO
Number of bits in internal arithmetic
operation
Number of clock signals in the design
Maximum clock frequency
Area of the chip
Power dissipation of the chip
Design Entry
Architectural decision Schematic Entry:
is to be taken first Place components
Number of sub- Interconnect
blocks, their components
functionality and Name IOs
interconnects
HDL Entry:
Type of processing,
serial or parallel Two dominant HDL:
VHDL
If pipelined, number
of stages and Verilog HDL
operation in each Describes digital
stage hardware as:
Design entry are of Structural Model
two types: Behavioral Model
Schematic entry In Verilog, each
variable can have 0,
HDL entry 1, x or z values
Functional Simulation
Verifies
the correctness of the design
There may be two types of errors:
Logic expression derived for implementing
a function may be erroneous.
Due to human error there may be
unconnected nets, undue duplication of
names or syntax error
To find errors and their location,
stimulus is given at the input and,
output response is observed.
Stimulus can be given as:
Test
vectors
Commands (by using command file)

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