Programmable Logic Devices

Lecture 1
MSc In Computer Engineering
Asst.Prof.Dr.Raghad Zuhair Yousif
Head of Computer Technics Engineering
Al-Kitab University College
Introduction
 PLDs

Programmable Logic Devices (PLD)

General purpose chip for implementing circuits
Can be customized using programmable switches

Main types of PLDs

PLA
PAL
ROM
CPLD
FPGA

Custom chips: standard cells, sea of gates

 Programmable Logic Devices
Programmable Logic Device (PLD) is an
integrated circuit with internal logic gates
and/or connections that can in some way be
changed by a programming process
Examples:
PROM
Programmable Logic Array (PLA)
Programmable Array Logic (PAL) device
Complex Programmable Logic Device (CPLD)
Field-Programmable Gate Array (FPGA)
A PLDs function is not fixed
Can be programmed to perform different
functions
Why PLDS?
Fact:
It is most economical to produce an IC in large
volumes
But:
Many situations require only small volumes of ICs
Many situations require changes to be done in the
field, e.g. Firmware of a product under development

A programmable logic device can be:

Produced in large volumes
Programmed to implement many different low-
volume designs
 PLD as a Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches
Used symbol in PLD

Multi-input OR gate There is a connection

There is no connection

conventional symbol array logic symbol

Most PLD technologies have gates with very

high fan-in
Fuse map: graphic representation of the
selected connections
Programmable Logic Devices (PLDs)

All use AND-OR structure- differ in which is programmable

Fixed
Programmable Programmable
Inputs AND array Outputs
connections OR array
(decoder)

Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
connections AND array OR array

Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
connections AND array connections OR array

Programmable logic array (PLA)

 Programmable Logic Array (PLA)
x1 x2 xn
Use to implement
circuits in SOP form
Input buffers
The connections in and
inverters
the AND plane are
programmable x1 x1 xn xn

P1
The connections in
the OR plane are AND plane OR plane
programmable Pk

f1 fm
Programmable Logic Array (PLA)

AND array and OR

array are programmable
XOR is available to
complement an output if
needed

Example:
3 inputs/2 outputs
F1 = A B + A C + A B C
F2 = (AC + BC)
 Gate Level Version of PLA
x1 x2 x3

Programmable
connections

f1 = x1x2+x1x3'+x1'x2'x3 OR plane
P1

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

AND plane

f1 f2
 Customary Schematic of a PLA
x1 x2 x3

OR plane
f1 = x1x2+x1x3'+x1'x2'x3
P1
f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

x marks the connections left in AND plane

place after programming
f1 f2
 Limitations of PLAs

PLAs come in various sizes

Typical size is 16 inputs, 32 product terms, 8 outputs
Each AND gate has large fan-in this limits the number of
inputs that can be provided in a PLA

16 inputs 316 = possible input combinations; only 32

permitted (since 32 AND gates) in a typical PLA

32 AND terms permitted large fan-in for OR gates as well

This makes PLAs slower and slightly more expensive than
some alternatives to be discussed shortly

8 outputs could have shared minterms, but not required

 Programmable Array Logic (PAL)
x1 x2 xn
Also used to implement
circuits in SOP form
Input buffers
The connections in and fixed connections
inverters
the AND plane are
programmable x1 x1 xn xn

P1
The connections in
the OR plane are AND plane OR plane
NOT programmable Pk

f1 fm
 Example Schematic of a PAL
x1 x2 x3

f1 = x1x2x3'+x1'x2x3

f2 = x1'x2'+x1x2x3 P1

f1
P2

P3

f2
P4

AND plane
Programmable Array Logic (PAL)

Fixed OR array and

programmable AND array
Opposite of ROM
Feed back is used to support
more product terms
AND output can not be shared
here!

Example:
4 inputs/4 outputs with fixed 3-
input OR gates
W = A B C + A B C D
X=?
Y=?
Z=?
 Comparing PALs and PLAs

PALs have the same limitations as PLAs (small

number of allowed AND terms) plus they have a
fixed OR plane less flexibility than PLAs

PALs are simpler to manufacture, cheaper, and

faster (better performance)

PALs also often have extra circuitry connected to the

output of each OR gate
The OR gate plus this circuitry is called a macrocell
 Macrocell

Select
Enable
OR gate from PAL 0
f1
1

D Q
Flip-flop
Clock

back to AND plane

 Macrocell Functions

Enable = 0 can be used to allow the output pin for f 1

to be used as an additional input pin to the PAL

Enable = 1, Select = 0 is normal

for typical PAL operation Select
Enable
0
f1
1
Enable = Select = 1 allows D Q
the PAL to synchronize the Clock

output changes with a clock

pulse back to AND plane

The feedback to the AND plane provides for multi-

level design
 Multi-Level Design with PALs

f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'

where g = BC + B'C' and C = h below
A B

Sel = 0
En = 0
0
1
h

D Q
Sel = 0
Clock En = 1
0
g
1

D Q
Select
Clock
0
f
1

D Q

Clock
Memory

Memory: A collection of cells capable of

storing binary information (1s or 0s) in
addition to electronic circuit for storing
(writing) and retrieving (reading) information.

n data lines (input/output)

k address lines
2k words (data unit)
Read/Write Control
Memory size = 2k X n
Memory (cont.)

Two Types of Memory:

Random Access Memory (RAM):
Write/Read operations
Volatile: Data is lost when power is turned
off
Read Only Memory (ROM):
Read operation (no write)
Non-Volatile: Data is permanent.
PROM is programmable (allow special write)
 ROM

A ROM (Read Only Memory) has a fixed AND plane

and a programmable OR plane

Size of AND plane is 2n where n = number of input

pins
Has an AND gate for every possible minterm so that all
input combinations access a different AND gate

OR plane dictates function mapped by the ROM

 4x4 ROM

22x4 bit ROM has 4 addresses that are decoded

2-to-4 decoder

a0

a1

d3 d2 d1 d0
Read-Only Memory (ROM)
ROM: A device in which permanent
binary information is stored using a
special device (programmer)

k inputs n outputs
(address)
2k x n ROM (data)

k inputs (address) 2k words each of

size n bits (data)
ROM DOES NOT have a write operation
ROM DOES NOT have data inputs
Word: group of bits stored in one location
ROM Internal Logic

The decoder Internal Logic of a 32x8 ROM

stage produces
ALL possible 0
minterms I0 1
2
32 Words of 8 I1 3
bits each 5-to-32 .
I2 decoder .
5 input lines I3
.
28
(address) 29
30
Each OR gate I4
31
has a 32 input
A contact can be
made using
fuse/anti-fuse A7 A6 A5 A4 A3 A2 A1 A0
 Programming a ROM

Inputs Outputs
I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 0 1 1 0 1 1 0 0 x x x x x
I0 1 x x x x
0 0 0 0 1 0 0 0 1 1 1 0 1
2 x x x x
0 0 0 1 0 1 1 0 0 0 1 0 1 I1
3 x x x x
0 0 0 1 1 1 0 1 1 0 0 1 0 I2 5-to-32 .
. . decoder .
.
. .
I3
28 x x
29 x x x x
. . I4
30 x x x
1 1 1 0 0 0 0 0 0 1 0 0 1 31 x x x x
1 1 1 0 1 1 1 1 0 0 0 1 0
1 1 1 1 0 0 1 0 0 1 0 1 0
1 1 1 1 1 0 0 1 1 0 0 1 1

A7 A6 A5 A4 A3 A2 A1 A0

Every ONE in truth table specifies a closed circuit

Every ZERO in truth table specifies an OPEN circuit
Example: At address 00011 The word 10110010 is
stored
 Combinational Circuit Implementation with ROM

ROM = Decoder + OR gates

Implementation of a combinational circuit is
easy
Store the truth table by programming the ROM
Only need to provide the truth table
Example 1

Example: Design a combinational circuit using ROM. The

circuit accepts a 3-bit number and generates an output
binary number equal to the square of the number.
Solution: Derive truth table:
Inputs Outputs

A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ

0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1 1

0 1 0 0 0 0 1 0 0 4

0 1 1 0 0 1 0 0 1 9

1 0 0 0 1 0 0 0 0 16

1 0 1 0 1 1 0 0 1 25

1 1 0 1 0 0 1 0 0 36

1 1 1 1 1 0 0 0 1 49
Example 1 (cont.)

Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49 B0

ROM truth table specifies the required connections

0 B1
A0 8 X 4 ROM B2
B1 is ALWAYS 0 no need to generate it using the ROM B3
A1
B0 is equal to A0 no need to generate it using the ROM
B4
Therefore: The minimum size of ROM needed is 2 3X4 or 8X4
A2 B5
Example 2

Problem: Tabulate the truth for an 8 X 4 ROM that implements the

following four Boolean functions:
A(X,Y,Z) = m(3,6,7); B(X,Y,Z) = m(0,1,4,5,6) 8 X 4 ROM A
X
C(X,Y,Z) = m(2,3,4); D(X,Y,Z) = m(2,3,4,7) B
Y
C
Z
Solution: D
Inputs Outputs
X Y Z A B C D
0 0 0 0 1 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 1
0 1 1 1 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 1 1 0 0
1 1 1 1 0 0 1
Example 3 (Size of a ROM)

Problem: Specify the size of a ROM (number of words and

number of bits per word) that will accommodate the truth table
for the following combinational circuit: An 8-bit
adder/subtractor with Cin and Cout.

Solution:
Inputs to the ROM (address lines) = 8 (first number) + (8
second number) + 1 (Cin) + 1 (Add/Subtract) 18 lines
Hence number of words in ROM is 218 = 256K
Size of each word = number of possible functions/outputs
= 16 (addition/subtraction) + 1 (Cout)
= 17

Hence ROM size = 256K X 17

 Sequential Circuit Implementation with ROM

inputs X Combinational outputs Z

Circuits
present state next state
FFs

sequential circuit = combinational circuit + memory

Combinational part can be built with a ROM as
shown previously
Number of address lines = No. of FF + No. of inputs
Number of outputs = No. of FF + No. of outputs
Example

Example: Design a sequential circuit whose state table is given, using a ROM and
a register.

State Table

We need a 8x3 ROM (why?)

3 address lines and 3 data lines

Exercise: Compare design with ROMs with the traditional design procedure.
 Types of ROMs
A ROM programmed in four different ways:
ROM: Mask Programming
By a semiconductor company
PROM (Programmable ROM)
User can blow/connect fuses with a special
programming device (PROM programmer)
Only programmed once!
EPROM (Erasable PROM)
Can be erased using Ultraviolet Light
Electrically Erasable PROM (EEPROM or
E2PROM)
Like an EPROM, but erased with electrical signal
 Programming SPLDs

PLAs, PALs, and ROMs are also called SPLDs

Simple Programmable Logic Devices

SPLDs must be programmed so that the switches

are in the correct places
CAD tools are usually used to do this
A fuse map is created by the CAD tool and then that map is
downloaded to the device via a special programming unit

There are two basic types of programming techniques

Removable sockets on a PCB
In system programming (ISP) on a PCB
This approach is not very common for PLAs and PALs but
it is quite common for more complex PLDs
 An SPLD Programming Unit

The SPLD is removed from the PCB, placed into the

unit and programmed there
 Removable SPLD Socket Package

PLCC (plastic-leaded chip carrier)

PLCC socket soldered to

the PCB
 In System Programming (ISP)

Used when the SPLD cannot be removed from the

PCB

A special cable and PCB connection are required to

program the SPLD from an attached computer

Very common approach to programming more

complex PLDs like CPLDs, FPGAs, etc.
 CPLD

Complex Programmable Logic Devices (CPLD)

SPLDs (PLA, PAL) are limited in size due to the

small number of input and output pins and the
limited number of product terms
Combined number of inputs + outputs < 32 or so

CPLDs contain multiple circuit blocks on a single

chip
Each block is like a PAL: PAL-like block
Connections are provided between PAL-like blocks via an
interconnection network that is programmable
Each block is connected to an I/O block as well
 Structure of a CPLD

I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block
 Internal Structure of a PAL-like Block

Includes macrocells
Usually about 16 each

PAL-like block
Fixed OR planes
OR gates have fan-in
between 5-20 PAL-like block

DQ
XOR gates provide
negation ability DQ

XOR has a control

DQ
input
 More on PAL-like Blocks

CPLD pins are provided to control XOR, MUX, and

tri-state gates

When tri-state gate is disabled, the corresponding

output pin can be used as an input pin
The associated PAL-like block is then useless

The AND plane and interconnection network are

programmable

Commercial CPLDs have between 2-100 PAL-like

blocks
 Programming a CPLD

CPLDs have many pins large ones have > 200

Removal of CPLD from a PCB is difficult without breaking
the pins
Use ISP (in system programming) to program the CPLD
JTAG (Joint Test Action Group) port used to connect the
CPLD to a computer
 Example CPLD

(x
f1ro
m
ixn
t2e
rx
c
o
n e
c
t
i3x
o
n w
i4x
r5e
s)x

6x
7u
n
se
dP
Use a CPLD to implement the function

A
L
-l0
ik
e
b
lo
c
kD
f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

0
Q1f
 FPGA

SPLDs and CPLDs are relatively small and useful for

simple logic devices
Up to about 20000 gates

Field Programmable Gate Arrays (FPGA) can handle

larger circuits
No AND/OR planes
Provide logic blocks, I/O blocks, and interconnection wires
and switches

Logic blocks provide functionality

Interconnection switches allow logic blocks to be connected
to each other and to the I/O pins
FPGA Design process
Design and implement a simple unit permitting to

Specification / Pseudocode
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in the
experiment 5, this time your unit has to be able to
perform an encryption algorithm by itself, executing
32 rounds..

On-paper hardware design

(Block diagram & ASM chart)

VHDL description (Your Source Files)

Library IEEE;

Functional simulation
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;

Synthesis Post-synthesis
simulation
FPGA Design process (2)
Implementation
Timing simulation

Configuration
On chip testing
 Structure of an FPGA

I/O block

interconnection
switch
I/O block

I/O block
logic block
I/O block
 LUTs

Logic blocks are implemented using a lookup table

(LUT)
Small number of inputs, one output
Contains storage cells that can be loaded with the desired
values

A 2 input LUT uses 3 MUXes

x
to implement any desired function 1
of 2 variables 0/1
Shannon's expansion at work!
0/1
f
0/1
0/1
x2
 Example 2 Input LUT

x1 x2 f
0 0 1 f = x1'x2' + x1x2, or using Shannon's expansion:
0 1 0
1 0 0 f = x1'(x2') + x1(x2)
1 1 1 = x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))

x1

1
0
f
0
1

x2
 3 Input LUT

7 2x1 MUXes and x1

8 storage cells are x2
required 0/1
0/1
Commercial LUTs have 0/1
4-5 inputs, and 16-32
0/1
storage cells f
0/1
0/1
0/1
0/1
x3
 Programming an FPGA

ISP method is used

LUTs contain volatile storage cells

None of the other PLD technologies are volatile
FPGA storage cells are loaded via a PROM when power is
first applied

The UP2 Education Board by Altera contains a JTAG

port, a MAX 7000 CPLD, and a FLEX 10K FPGA
The MAX 7000 CPLD chip is EPM7128SLC84-7
EPM7 MAX 7000 family; 128 macrocells; LC84 84 pin
PLCC package; 7 speed grade
 Example FPGA

x
3 f

Use an FPGA with 2 input LUTS to implement the

x
function f = x1x2 + x2'x3

1x0f x 0
1
f
x
2x1
10
1 x 2 2
f1 = x1x2

2 3
f2 = x2'x3
f = f1 + f2

ff120
1
f
 Another Example FPGA

Use an FPGA with 2 input LUTS to implement the

function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

Fan-in of expression is too large for FPGA (this was simple

to do in a CPLD)

Factor f to get sub-expressions with max fan-in = 2

f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5)
= (x1x6' + x2x7)(x3 + x4x5)

Could use Shannon's expansion instead

Goal is to build expressions out of 2-input LUTs
 x
4x5x3f
FPGA Implementation

x
f = (x1x6' + x2x7)(x3 + x4x5)

1
x
66x
0
A
1
0
1 x
0
C
1
4
5 x
0
1
C
3E
x
2
x
77x
0
B 0
A
1
D
1B E
2 0
D
1f
 Custom Chips

PLDs are limited by number of programmable

switches
Consume space
Reduce speed

Custom chips are created from scratch

Expensive used when high speed is required, volume
sales are expected, and chip size is small but with high
density of gates
ASICs (Application Specific Integrated Circuits) are custom
chips that use a standard cell layout to reduce design costs
 Standard Cells

Rows of logic gates can be connected by wires in

the routing channels
Designers (via CAD tools) select prefab gates from a library
and place them in rows
Interconnections are made by wires in routing channels

ff21
Multiple layers may be used to avoid short circuiting

x

A hard-wired connection between layers is called a via

1
x
2
3
 Example: Standard Cells

x ff21
f1 = x1x2 + x1'x2'x3 + x1x3'

1
f2 = x1x2 + x1'x2'x3 + x1x3

x
2
3
 Sea of Gates Gate Array

A Sea of Gates gate array is just like a standard cell

except all gates are of the same type
Interconnections are run in channels and use multiple
layers
Cheaper to manufacture due to regularity
 Example: Sea of Gates

f1 = x2x3' + x1x3
black bottom
layer channels

red top layer channels

 Digital Logic Technology Tradeoffs

Full custom
VLSI design

ASICs
Speed / Density /
Complexity / Likely
Market Volume CPLDs
FPGAs

PLDs

Engineering cost / Time to develop