LUN VN TT NGHIP I HC

GIAO TIP SD_CARD V MN HNH VGA

DNG NIOS II

GVHD : Th.s Bi Quc Bo

SVTH : Nguyn Dng Thanh Lm

30-6-2009
MC TIU HON THNH

Xy dng h thng trn Kit DE2

giao tip vi SD CARD v c d liu
file nh bitmap lu vao SRAM.
Kt qu thu c l hin th cc file nh
thng qua cng VGA ln mn hnh vi
tnh.
Tng quan

ti: Giao tip SD_CARD v mn

hnh VGA dng NIOS II.
Ni dung gm 2 phn chnh:
Xy dng h thng phn cng.
Vit chng trnh c th nh, x l file nh
v iu khin h thng
 Phn I
Xy Dng h thng phn cng
Tng quan kt ni
I Onchip
memory
II

LEDR SDRAM SDRAM

Control Chip

SW CPU_NIOS II

SRAM
SRAM_data (in) Chip

display
RAM_data_out

> CLK RAM

40.000 byte

R
8'hFF
VGA_control

VGA
Chip
G;B
16'hFFFF
Kt ni chi tit
RAM_WE WE
RAM_data_in [7:0] Read_data
RAM_write_addr [15:0] Write_addr

RAM_read_addr [15:0] 0 Data [7:0]

C0 100M
[15:0] Read_addr
CLOCK_50 PLL C1 50M [15:0]
1
RAM_data_out
CLK RAM (RED)
C2 50M (-3ns)
display

CPU_NIOS II
Vi khi PLL: SRAM_WE_N SRAM_WE_N
C2: To ta xung Clock 50Mhz
c tr pha -3ns (sm 3ns) so vi xung
50Mhz (C1). to tn hiu clk cho SDRAM SRAM_DATA (out) [15:0] 0
Nu khng to tn hiu C2 ny th khi NIOS
SRAM_DQ
giao tip vi SDRAM s b bo li clock_skew
16'hzzzz 1

SRAM
SRAM_DATA (in) [15:0]
(G,B)
SRAM_ADDR [17:0] 0
> CLK
[17:0] SRAM_ADDR
[15:0] 1

1
8'hFF 0 SRAM_CE_N
0
Color_red VGA_addr 0 SRAM_OE_N
1 0 SRAM_UB_N
0 SRAM_LB_N
16'hFFFF 0
Color_green
[15:8]
[15:0] 1
Color_blue
VGA_control R [9:0] R VGA chip
[7:0]
G [9:0] G ADV7123
B [9:0] B
VGA_HS HS
VGA_VS
> CLK VS

0 SYS

> CLK
Danh sch cc khi (1/2)
CPU_NIOS II: iu khin hot ng cc khi
v x l hnh nh.
Onchip_memory: cha lnh (code) v
d liu.
VGA_control: To tn hiu giao tip v iu
khin VGA chip.
RAM: c dng cha d liu Red ca
hnh nh.
Danh sch cc khi (2/2)
SRAM: Cha d liu nh gc, nh x l
v l b m (buffer) cho VGA chip.
SW: ng vai tr l cc tn hiu iu khin.
LEDR: Hin th cc kt qu cn kim tra
trong cc bc kim tra.
PLL: To ra cc xung clock cp cho hot
ng ca cc khi
PLL

inclk0: Clock ng vo. Tn s 50Mhz

C0: 100Mhz cp cho b nh RAM, v clock ca
VGA chip ng b d liu ca b m bean
trong chip.
C1: 50Mhz cp cho hot ng ca CPU.
C2: To ta xung Clock 50Mhz c tr pha -3ns
Khi CPU
Cc port ca h thng CPU
Clk:
reset_n:
out_port_from_the_Display:
in_port_to_the_KEY:
out_port_from_the_LEDR:
in_port_to_the_SW:
Cc port ca CPU giao tip
vi RAM
out_port_from_the_RAM_DATA_in
in_port_to_the_RAM_DATA_out
out_port_from_the_RAM_RD_ADDR
out_port_from_the_RAM_WE
out_port_from_the_RAM_WR_ADDR
Cc port ca CPU giao tip
vi SRAM
out_port_from_the_SRAM_ADDR
in_port_to_the_SRAM_DATA
out_port_from_the_SRAM_DATA
out_port_from_the_SRAM_WE_N
Cc port ca CPU giao tip
vi SDRAM
zs_addr_from_the_sdram Cc Port ny
zs_ba_from_the_sdram do Quartus t
zs_cas_n_from_the_sdram to khi ta
zs_cke_from_the_sdram thm b
zs_cs_n_from_the_sdram SDRAM_cont
zs_dq_to_and_from_the_sdram
roller vo h
zs_dqm_from_the_sdram
thng SoPC
zs_ras_n_from_the_sdram
zs_we_n_from_the_sdram
VGA_control
Nhim v:
ng b ha d liu mu bng cc to ra cc tn
hiu ng b H_S v V_S.
Kch thc ton mn hnh l 640*480.
To khung (ca s) hin th hnh nh. Kch thc
khung 180*180.
Pht hin VGA chip ang qut ti vng trong ca
s hin th th a ra d liu nh
Vng ngoi ca s hin th a ra d liu 0x00
hin th mu en.
Cch xy dng VGA_control
Da vo tn hiu m theo hng v ct
ng b tn hiu qut (s dng code trn
trang web ca altera).
Tn s s dng trong khi VGA: 50Mhz
if(h_count>=1318 & h_count<=1510) HS<=0;
else HS<=1;

if(v_count<=494 & v_count>=493) VS<=

else VS<=1;
Cch xy dng VGA_control
To ra tn hiu pic_en quan st khi no
VGA_Chip ang qut trong vng hin th hnh
nh:

if(h_count>=400 & h_count<798 & v_count >= 151 & v_count < 350)
pic_en <= 1;
else
pic_en <= 0;

assign color_R_t = pic_en ? color_R : 8'h00;

assign color_G_t = pic_en ? color_G : 8'h00;
assign color_B_t = pic_en ? color_B : 8'h00;
Cch xy dng VGA_control
Xy dng cng thc tnh a ch truy cp
vo cc vng buffer
VGA_addr = (200 - (v_count - 150))*200 + (h_count- 200)

(200; 350) (400; 350)

Khung nh (ca s)
hin th

(200; 150) (400; 150)

SRAM
0x00000

Cha d liu 16 bit mu Buffer m cho

VGA
B, G ca nh . (G,B)

0x3FFFF
Xy dng phn cng giao
tip SRAM

SRAM_WE_N

15:0 15:0
out_port_to_the_SRAM_DQ SRAM_DQ

NIOS II
15:0
in_port_to_the_SRAM_DQ SRAM

17:0
SRAM_ADDR
out_port_to_the_SRAM_ADDR
S dng SRAM lm b m
d liu cho VGA
C hnh phng
SRAM_WE_N
to trn giy A1
15:0 15:0
out_port_to_the_SRAM_ SRAM_D
DQ Q

15:0
in_port_to_the_SRAM_
DQ NIOS II
DISPLAY
15:0
SRAM
out_port_to_the_SRAM_AD
DR 0 15:0
SRAM_AD
15:0 DR
DISPLAY VGA_ADD 1
R
9:0
G G
0 9:0
FFFF VGA B B
control
G,B H_S H_S
VGA
1 V_S V_S
Chip
Lu gii thut c v ghi SRAM
Write
Read

DISPLAY = 0

DISPLAY = 0
SRAM_WE_N = 1

SRAM_WE_N = 1
SRAM_ADDR = addr

SRAM_ADDR = addr
SRAM_DQ = data

Wait some clock

SRAM_WE_N = 0

Read data from PIO

Wait one clock
SRAM_DQ

SRAM_WE_N = 1
Ret

Ret
RAM
c xy dng bng chc nng Mega
Wizard Plug_in manager trong Quartus II.
Cu to t cc b nh bn trong FPGA
(M4K).
c v ghi RAM
Ghi RAM
c RAM
a a ch

a a ch Xut d liu

Wren = 1

c d liu
Wait one clock

RET
Wren = 0

RET
S kt ni ca RAM vi
CPU v VGA_control
Clk_100
clock
RAM_WE wren
7:0
RAM_DATA_in data
15:0
Write_add wraddress
r
7:0
RAM_DATA_out q
NIOS II
DISPLAY
15:0
RAM
read_add
r 0 15:0
rdaddress
15:0
DISPLAY VGA_ADD 1
R

0 9:0
FF VGA R R
R control
H_S H_S
VGA
1 V_S V_S
Chip
Cc khi cn li
Onchip memory: c dng lm b nh
cha code v data cho CPU. Nhng v b
nh ny nh v khng nn ta phi m
rng b nh bng SDRAM.
giao tip vi SDRAM chip ta cn to thm
b SDRAM_controller
C hai khi Onchip_memory v
SRAM_controller u do chng trnh SoPC
xy dng.
 Phn II
Xy dng v thc hin gii thut
x l nh
S gii thut chnh
MAIN

display_original()

x=
 int show_ pro( int a)

x = SW

Gi nguyn gi tr
x=?
Thay i gi tr
0 1 2 3z 4 5 6

display_
original

a=x

return a
Hin th nh trong vng nh nh
x l
hin th nh x l ta phi chp ton b
d liu ca phn 1 vo vng buffer G,B v
chp ton b d liu ca phn 2 vo vng
buffer R. Sau cho DISPLAY = 1.
Hng pht trin ti
H thng trn cn c th thc hin:

Do thi gian lm lun vn c hn. Nn em
ch c th thc hin c cc chc nng
nh trnh by.
Hn ch ca ti
V gii hn b nh trn kit DE2 nn ta khng
th thc hin c cc nh c kch thc
ln hn.