INTERFACING

8255 PPI (Programmable Peripheral Interface)

It
is an I/O port chip used for interfacing I/O
devices with microprocessor
Very commonly used peripheral chip
Knowledge of 8255 essential for students in
the Microprocessors lab for Interfacing
experiments
 3
PPI
Programmable Peripheral interface -8255

Features:
Designed by Intel to interface with 8,16 bit & higher
capability microprocessor with I/O peripherals
It has 24 I/O lines which may be programmed in to two
groups of 12 lines or three groups of 8 lines
The two group I/O pins named as GROUP A and GROUP
B
Each group contains a two sub group of 8 bit I/O lines & 4
bit I/O lines
Group A contains an 8 bit port A along with a 4 bit port C
called Cupper
Group B contains an 8 bit port B along with a bit port C
called C
8255 Pin diagram
PA7-PA0 buffered/latched i/o 8 bit PORT A
PB7-PB0 buffered/latched i/o 8 bit PORT B
PC7-PC4 Upper nibble of PORT C
PC3-PC0 Lower nibble of PORT C
RD Read
WR-Write
CS-Chip Select
A0-A1 Address Lines
D0-D7 Data Lines carries DATA or Control
Word to/from processor
RESET Clears control word registers
Data Bus Buffer
This bi-directional 8-bit buffer is used to interface the 8255
to the system data bus.
Data is transmitted or received by the buffer upon execution
of input or output instructions by the CPU.
Control words information is transferred through the data
bus buffer.
Read/Write and Control Logic
This block is to manage all of the internal and external
transfers of both Data and Control words
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups
(CS) Chip Select
A "low" on this input pin enables the communication
between the 8255 and the CPU
(RD) Read
A "low" on this input pin enables 8255 to send the data
or status information to the CPU on the data bus
(WR) Write
A "low" on this input pin enables the CPU to write data
or control words into the 8255
(A0 and A1) Port Select 0 and Port Select 1
These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the
control word register
There is also a Control port from the
Processor point of view.
Its contents decides the working of
8255.
When CS (Chip select) is 0, 8255 is
selected for communication by the
processor.
The chip select circuit connected to the
CS pin assigns addresses to the ports
of 8255.
Control Word Register
8255 Modes of Operations
There are 2 basic modes of operations
I/O Mode (Mode 0,Mode1 & Mode2)
Bit Set Reset mode (BSR)

In I/O mode: 8255 works as programmable

I/O ports.
In BSR : Only port C (PC0-PC7) can be used
to set /reset its individual port bits.
 BSR Mode
In this mode any of the 8 bit of port C can be set or reset
depending on D0 of the control word
The bit to be set or reset is selected by D1,D2 & D3 of the
control word register
Eg: If the 5th bit (PC5) of port C has to be "SET", then what is the control
word?
1. Since it is BSR mode, D7 = '0'.
2. Since D4, D5, D6 are not used, assume them to be '0'.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
4. PC5 has to be set, hence, D0 = '1'.

Applying the above values to the format for BSR mode, we

get the control word as "0B (hex)".
Mode 0(Basic I/O mode)
Features of this mode

Two 8-bit ports ( port A and port B )and two 4-bit ports (port
C upper and lower ) are available. The two 4-bit ports can be
Collectively used as a third 8-bit port.

Any port can be used as an input or output port

Output ports are latched. Input ports are not latched

A maximum of four ports are available so that overall 16 I/O

configuration are possible.

All these modes can be selected by programming the Control

word register. CWR has two formats one for BSR mode and
I/O modes
 I/O mode

D7 D6 D5 D4 D3 D2 D1 D0

(1=I/O GA mode select PA PCU GB mode PB PCL

) select

D6, D5: GA mode select: Mode 0: No interrupts.

Plain I/O. Two 8 bit ports PA, PB.
00 = mode0
Two 4 bit ports PCU and PCL.
01 = mode1 Outputs latched, inputs buffered.

1X = mode2 GA- Group A GB-Group B

D4(PA), D3(PCU): 1=input 0=output

D2: GB mode select: 0=mode0, 1=mode1
D1(PB), D0(PCL): 1=input 0=output
 16-bit data bus to 8-bit peripherals

The problem associated with connecting the 8-bit

interface device to a 16-bit bus of an 8086 are releted to
need to transfer even-addressed bytes over the lower
half of the data bus and odd-addressed bytes over the
upper half.

BHE# A0 Transfer
0 0 Not useful
0 1 Odd addressed byte on upper half of bus
1 0 Even addressed byte on lower half of bus
1 1 Not possible
Solution 1: Use only even addresses

Example: We want to use a 8255 PPI with the

starting I/O address of F8h. Use even adresses
only.
A7 A6 A5 A4 A3 A2 A1 A0
f8h 1 1 1 1 1 0 0 0 B : Port A
fah 1 1 1 1 1 0 1 0 B : Port B
fch 1 1 1 1 1 1 0 0 B : Port C
feh 1 1 1 1 1 1 1 0 B : Control Reg.

Register Select
 Circuit Diagram

D0-D7 D0-D7

A3 A0 8255
0
A4 A1 1

From A5 A2 2 PPI
138 3

CPU M/IO# E1
4
5
A0 E2 6
E3 7 CS
A7
A6
IORDC# RD#
IOWRC# WR#
A2 A1
A1 A0
 Access to Interface Registers
Port B and C are programmed as Mode 0 input port.
Port A is programmed as Mode 0 simple latched output
port.
Write a code to implement the operation
PortA=PortB-PortC

mov AL,08Bh ;control word

out 0FEh,AL ;written to control reg.
in AL,0FCh ;Read Port C
mov BL,AL ;
in AL,OFAh ;Read Port B
sub AL,BL ;PortB-PortC
out 0F8h,AL ;write PortA
Solution 2: Use only odd addresses

Example: We want to use a 8255 PPI with the

starting I/O address of F9h. Use odd adresses
only.
A7 A6 A5 A4 A3 A2 A1 A0
f9h 1 1 1 1 1 0 0 1 B : Port A
fbh 1 1 1 1 1 0 1 1 B : Port B
fdh 1 1 1 1 1 1 0 1 B : Port C
ffh 1 1 1 1 1 1 1 1 B : Control Reg.

Register Select
 Circuit Diagram

D8-D15 D0-D7

A3 A0 8255
0
A4 A1 1

From A5 A2 2 PPI
138 3

CPU M/IO# E1
4
5
A0 E2 6
E3 7 CS
A7
A6
IORDC# RD#
IOWRC# WR#
A2 A1
A1 A0
 Solution 3: Use consecutive even
and odd address

Example: We want to use a 8255 PPI with the

starting I/O address of C0h. Use even and odd
adresses.
A7 A6 A5 A4 A3 A2 A1 A0
C0h 1 1 0 0 0 0 0 0B : Port A
C1h 1 1 0 0 0 0 0 1B : Port B
C2h 1 1 0 0 0 0 1 0B : Port C
C3h 1 1 0 0 0 0 1 1B : Control Reg.

Register Select
 D8-D15
BHE#
74
245

OE#
Y0
D0-D7
D0-D7
74
245

OE# 8255
PPI
A4 A0 CS
0
A3 A1 1
A2 A2 2
From 138 3
4
CPU M/IO#
A5
E1 5
E2 6
E3 7
A7
A6
IORDC#
RD#
IOWRC#
WR#
A1
A1
A0
A0
Example - Port addresses
Solution
Example Programming 8255
 8255 PPI Contd.
Mode 0: Simple Input or Output

In this mode, ports A, B are used as two simple 8-bit I/O ports
port C as two 4-bit ports.
Each port can be programmed to function as simply an input port or
an output port. The input/output features in Mode 0 are as follows.

1. Outputs are latched.

2. Inputs are not latched.

3. Ports dont have handshake or interrupt capability.

35
 8255 PPI Contd.
Mode 1: Input or Output with Handshake
In this mode, handshake signals are exchanged between the MPU
and peripherals prior to data transfer.
The features of the mode include the following:
1. Two ports (A and B) function as 8-bit I/O ports.
They can be configured as either as input or output
ports.
2. Each port uses three lines from port C as handshake
signals.
The remaining two lines of Port C can be used for simple
I/O operations.
3. Input and Output data are latched.
4. Interrupt logic is supported. 36
Mode 1 (Strobed I/O mode)
In this mode hand shaking signals controls the i/o operation
Port C lines PC0,PC1 & PC2 provides the handshake signals
for port B
Port C lines P3,PC6 & PC7 provides the handshake signals for
port A
PC4 & PC5 can be used as independent I/O lines

Input Control Signal Definitions

STB(Strobe input) : when it is low, data from the data lines are
loaded into the latches (PC4)
IBF (Input buffer full):if it rises high, indicates data loaded into
latches ( Acknowledgement ) (PC5).
INTR-to interrupt CPU,when ever an input device request
the service(PC3)
Mode control Group A and B
Input control signal M1
 MODE 1 EXAMPLE:
Interface a key board and printer to 8086 through
8255.Use handshaking. Connect printer to Port A and
Keyboard Port B Write necessary ALP.
 Transfer of the ASCII codes from a
microcomputer to a printer must be done
on a handshake basis because the
microcomputer can send characters much
faster than a printer can print them.
 Printer Operation
Printer Initialized by INIT,
First of all the printer should be initialized by a 50
S (minimum) pulse on the INIT pin of the printer.
Then BUSY pin is to be to confirm if the printer is
ready. If this signal is low, it indicates that the
printer is to accept a character from the CPU.
ASCII code of the character to be printed is sent
on the eight parallel port lines.
Once the data is sent on eight parallel lines, the
STROBE signal is activated after at least 0.5s
 The falling edge of the STROBE signal causes
the printer to make its BUSY pin high,
Indicating that the printer is busy.
A low on the BUSY pin further indicates that
the printer is ready to accept the next
character.
Timing waveform of data transfer to a Printer
 00F0H PORT A
00F2H PORT B

00F4H PORT C

00F6H CONTROL
0000 1000
Out put control signal definition(Mode 1)
OBF(output buffer full)-when low,it indicates the CPU has
written data to output port

ACK(Acknowledge input)-given by output device

INTR -interrupt to CPU when output device acknowledge the

data received
Mode 2(Strobed bi directional I/O)
Only 8 bit in group A is available
The 8 bit port A is bidirectional & have 5 bit port control
lines(PC3-PC7)
3 I/O lines are available at port C (PC2-PC0)
 8254 Software
Programmable Timer
/Counter
 8253 & 8254 Operations

Intel 8253 & 8254 8253 8254

contains 16 bit
counters

I/p clock I/p clock

frequency frequency 8
2.6Mhz Mhz
Have Read Doesnt
back feature have read
back feature
 8254
Contains 3 16-bit software
programmable counter (load, start,
stop by instructions in program )
8 bit data bus interface
CS(Chip Select) i/p to assert address
decoder
2 address i/p A0 & A1
8 Mhz clock i/p(CLK)
GATE i/p external signal to start /
stop counter
GATE = 1 Counter enable counting
GATE = 0 Counter disable
OUT pin O/P signals
 Working modes of 8254/8253

Mode 0-Interrupt on terminal

count
Mode 1-Programmable one shot
Mode 2- Rate generator
Mode 3-Square wave generator
Mode 4-Software triggered strobe
Mode 5-Hardware triggered strobe
Mode 0 Interrupt on terminal count

After the Control Word is written, OUT

is initially low, and will remain low until
the Counter reaches zero

OUT then goes high and remains high

until a new count

GATE = 1 enables counting

GATE = 0 disables counting

 After the Control Word and initial count are
written to a Counter, the initial count will be
loaded on the next CLK pulse.

This CLK pulse does not decrement the

count, so for an initial count of N, OUT does
not go high until N a 1 CLK pulses after the
initial count is written.
Mode 0
Mode 1-Hardware retrigger able
one shot

OUT will be initially high.

OUT will go low on the CLK pulse

following a trigger(Gate) to begin
the one-shot pulse, and will
remain low until the Counter
reaches zero.
 After writing the Control Word and initial
count, the Counter is armed. A trigger
results in loading the Counter and
setting OUT low on the next CLK pulse,
thus starting the one-shot pulse.
An initial count of N will result in a one-
shot pulse N CLK cycles in duration. The
one-shot is retriggerable, hence OUT will
remain low for N CLK pulses after any
trigger. The
one-shot pulse can be repeated without
rewriting the same count into the
counter. GATE has no effect on OUT.
Mode1
 Mode 2- Rate generator

This Mode functions like a divide-by-N counter. It is

typically used to generate a Real Time Clock
interrupt.

OUT will initially be high. When the initial count has

decremented to 1, OUT goes low for one CLK pulse.

Mode 2 is periodic; the same sequence is repeated

indefinitely

GATE = 1 enables counting; GATE = 0 disables

counting.
Mode 2
 Mode 3-Square wave generator

It mode is similar to mode

2,when the count N is even
then for half of the count
the OUT remains high and
remains low for next half
Odd number : First pulse is
high then (N-1)/2 will be
square . High sequence will
Mode 3
 Mode 4-Software triggered strobe

OUT will be initially high. When the initial

count expires,OUT will go low for one CLK
pulse and then go high again.

The counting sequence is ``triggered' by

writing the initial count.

GATE =1 enables counting

GATE = 0 disables counting

Mode 4
 Mode 5-Hardware triggered strobe

OUT will initially be high. Counting is

triggered by a rising edge of GATE.

When the initial count has expired, OUT will

go low for one CLK pulse and then go high
again.
Mode 5
 Initializing 8254 Programmable
Peripheral device
First power turned on 8254 undefined states.
To initialize follow the steps below
1. Determine system base address
2. From the truth table system base
address of the 8254 is FF01H
 Initializing 8254 Programmable
Peripheral device
2. Use the device data A1 A0 SELECTS
sheet to determine
the internal address 0 0 COUNTER0
of the control
registers, ports , 0 1 COUNTER1
timer , status
register , etc in the 1 0 COUNTER2
device.

1 1 Control Word
Register
 Initializing 8254 Programmable
Peripheral device
3. Add each of the internal addresses to the
system base address to determine the
system address of each of the parts of the
device. Note : addresses should be odd to connect
upper half of the data bus

SYSTEM BUS 8254 PART

F F 0 0 COUNTER0
F F 0 3 COUNTER1
F F 0 5 COUNTER2
F F 0 7 CONTROL REG
 Control word formats

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

SC1 SC0
0 0 SELECT COUNTER 0
0 1 SELECT COUNTER1
1 0 SELECT COUNTER2
1 1 READ BACK
COMMAND
 RW-READ/WRITE

RL1 RL0
0 0 COUNTER LATCH COMMAND
0 1 READ/WRITE LSB ONLY
1 0 READ/WRITE MSB ONLY
1 1 READ/WRITE LSB FIRST THEN
MSB
 M-MODE

0 0 0 MODE0-int on terminal
count
0 0 1 MODE1-H/W one shot
X 1 0 MODE2- Pulse generator
X 1 1 MODE3- Square wave gen
1 0 0 MODE4- S/W triggered
strobe
1 0 1 MODE5-H/W triggered
strobe
 BCD

0 COUNTER (HEX)
1 BINARY CODED DECIMAL
System Interface
 f=1.5MHz,
T=1/1.5 X10-6=0.66 s
 ii. For generating interrupt to the processor
after10ms, the 8253 is to be used in mode 0.
The OUT1 pin of 8253 is connected to
interrupt input of the processor.
Let us use counter 1 for this purpose, and
operate the 8253 in HEX count mode.
 Number of T states required for 10ms delay
=10X10-3
/0.66x10-6
=15x103 =15000 states =3A98H
 iii. For generating a 5ms quasistable state
duration, the count required is calculated first.
The counter 2 of 8253 is used in mode1, to
count in binary. The OUT2 signal normally
remains high after the count is loaded, till the
trigger is applied. After the application of
trigger signal, the output goes low in the
next cycle, count down starts and whenever
the count goes zero the output again goes
high.
 8251 -USART

Serial I/O - Programmable Communication Interface

 Data Communications
Data communications refers to the ability of one computer
to exchange data with another computer or a peripheral
Standard data communication interfaces and standards are
needed
Centronics parallel printer interface
RS-232 defines a serial communications standard
8251 USART (Universal Synchronous/Asynchronous
Receiver/Transmitter) is the key component for converting
parallel data to serial form and vice versa
Two types of serial data communications are widely used
Asynchronous communications
Synchronous communications
Types of Transmission
 Asynchronous Communications
Eliminates the need for a clock signal between
two microprocessor based systems
Transmit data

Receive data
System 1 System 2
Signal common
 Asynchronous Communications
Data to be transmitted is sent out one
character at a time and the receiver end of the
communication line synchronization is
performed by examining synchronization bits
that are included at the beginning and at the
end of each character
Introduction to serial data transfer

- within a microcomputer data is transferred in parallel

because it is the fastest way

- for long distances, data is sent from parallel to serial form,

so that it can be sent on a single wire.

- serial data received from a distance source is converted to parallel

form, so that it can be easily be transferred on the microcomputer

- for sending the data over long distances, the standard telephone
system is a conventional path, because the wiring and connections
are already in place.

- It is enough to convert digital signals to audio-frequency tones,

which are in the frequency range that the phone lines can transmit.

- The device used to do this conversion is modem

 Digital data transmission using modems and phone lines

Microcomputer Terminal computer

controlled terminal MODEM MODEM

TxD TxD

RxD Telephone RxD

line
RTS* RTS*

CTS* CTS*

CD* CD*

DTR* DTR*

DSR* DSR*
DTE DCE DCE DTE

DTE=Data terminal equipment

DCE=Data communication equipment
Data and handshaking signals
When the terminal is switched on, it asserts Data-
Terminal-Ready (DTR*) to tell the modem it is ready

Modem asserts Data-Set-Ready (DSR*) to the

terminal when it is ready to transmit and receive
data.

When the terminal has a character ready to send, it

will assert Request-To-Send (RTS*) signal to modem

The modem will send Carrier-Detect (CD*) signal to

the terminal indicating a connection establishment
 When the modem is fully ready to transmit data it will assert
a Clear-
To Send signal (CTS*) back to the terminal

The terminal then sends serial data characters to modem.

When the terminal has sent all the characters, it makes its
RTS* signal high.

This
cause the modem to unassert CTS* signal and stop
transmitting.

A similar handshake occurs between modem and computer at

the other end.
8251 block diagram
 D7-D0 connect to system data bus, so that data and
control words
can be transferred
CS*-to select the chip
8251 has two internal addresses, a control
address(FFF2H) which is selected when C/D* is high
and a data address (FFF0H)when the C/D* is low
RD*,WR*,& RESET are connected to the system
signals
The shift registers in USART require clocks
TXC,RXC transmitter clock and receiver clock for
shifting the data
TXD- indicates serial-data output
RXD-indicates serial-data input
 8251A is double buffered.
- one character can be loaded into a holding buffer
while another
character is shifted out of the transmit shift
register
TxRDY: Transmitter ready- this output from 8251 will
go high when the holding buffer is empty and
another character can be sent from CPU.
TxEmpty: Transmitter buffer empty- this output will
go high when the holding buffer and transmit shift
register are empty.
RxRDY: Receiver ready will go high when a
character is has been shifted into the receiver buffer
and is ready to read out by the CPU.
SYNDET/BD-Sync detect /Break detect
1) When programmed for synchronous
data transmission, this pin will go high when
the 8251A finds a specified sync characters in
the incoming string
2) When programmed in asynchronous
mode, this pin will go high if RxD stays low for
more than two character times. This indicates
an intentional break in data transmission.
CONTROL WORDS
There are two types of control word and
a status word
1. Mode word
2. Command word
3. Status word
Mode Word-Asynchronous
Mode Word Synchronous
Command Word
 Status Word

D0-Indicates USART is ready to accept a data character

D1-indicates USART has received the Character and ready to transfer it to
the CPU
D2-indicates parallel to serial converter is empty
D3-Parity error
D4-Over Run error-Indicates CPU does not read a character before the
next one becomes available
D5-Framing Error-Set when valid stop is not detected
D6-Sync Detect-Indicates that the character sync has been achieved
D7-used to test modem condition
 DMA controller 8257
Direct Memory Access--the ability of an I/O subsystem to transfer data to
and from a memory subsystem without processor intervention.

DMA Controller--a device that can control data transfers between an I/O
subsystem and a memory subsystem in the same manner that a processor
can control such transfers
DMA Controller Interfaced with the
CPU
 Features of 8257
It is programmable,4 channel direct memory access controller

Each channel can programmed individually

Each channel has a pair of 16 bit registers viz DMA address register and
terminal counter registers

Address register gives the address of the memory location & counter
specifies the number DMA cycles to be performed

It maintains a DMA cycle count for each channel and activates the TC
signal to indicate the peripheral that specified DMA cycles are completed
 Pin Configuration
It has priority logic that resolves the
peripheral request. Can be programmed
in two modes either fixed or rotating mode

D0-D7( Bidirectional pins connected

to system bus

Address Bus(A0-A3 & A4-A7)

Address Strobe (ADSTB)-used to

demultiplex higher byte address and
data using external latch
 Address Enable (AEN)-indicates available of higher address on the latches

Memory Read/Memory Write(MEMR,MEMW)

I/O Read / I/O Write (IOR,IOW)

Chip Select(CS)

Hold Request(HRQ)-it is used for requesting the CPU to get the control of
the system bus

Hold Ack(HLDA) -indicates that CPU has granted the system bus
 DREQ0 DREQ3 -these are DMA request

DACK0-DACK3 these are the ack for DMA request

Terminal Count it indicates the completion of DMA cycle

Architecture of 8257
 Data buffers-there is a 8 bit buffer which interface the 8257 to
system bus.
In slave mode, it is used to transfer data between CPU and internal
registers of 8257
In master mode, it is used to send higher byte address on the data
bus
DMA Channels:
8257 has 4 separate channels CH0 to CH1.each channel has a pair
of 2 16 bit registers.
Also there are two common register for all the channels namely
mode set & status registers
CPU selects one of these 10 registers using address lines A0-A3
 DMA address register- used to store the starting address of the
memory location

Terminal Count registers lower 14 bits are used count the required
number of DMA cycles

DMA CYCLES:
DMA Read:Data is transferred from memory to I/O devices
DMA write:Data is transferred from I/O device to memory
DMA Verify:Data is not transfer,Used by peripheral device to verify the data that has
been recently transferred .
 Mode Register

Use of mode register

1. Enable/disable a channel.
2. Fixed/rotating priority
3. Stop DMA on terminal count.
4.Extended/normal write time.
5. Auto reloading
 B0-B3 bits enable one of the four DMA channels

B4(Rotating priority) - is set enables rotating priority otherwise

normal

B6 (TC) -bit is set selected channel is disabled after the terminal

count condition is reached & further prevents any DMA cycle on the
channel

If the TC stop bit is set to zero the channel is not disabled even after
the count reaches zero
 B7- auto load bit is set enables channel 2 for repeat block chaining
operation.

Channel 2 register are reloaded with the corresponding channel 3

register for the next block transfer

B6 (Extended write)- if set then extends the duration of MEMW and

IOW.used while interfacing with slow devices.
 Status Register

Update flag is set when ch2 count reg is updated with the ch3 count reg
value

Rotating Priority
 Example
Write an Initialization program to transfer of data from a peripheral to
memory for the following specification
1)Bytes to be transferred is 256 bytes
2)Memory starting address is 2050
3)Channel used is ch1
4)Priority Rotating
5)Extended write disabled
6)TC Stop Enabled
7)Addresses:
Mode set register is 88H
DMA address Register of Ch1 is 82H
Terminal Count Register of ch1 is 83H
 Solution:
Mode set Command word:
0101 0 0 1 0= 52H

Terminal Count Register:

0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1=40FFH

256 bytes-1=255 count in hex is 0FFH

DMA Write Cycle (i.e) =0 1
 Program:
MOV AL,50H
OUT 82,AL
MOV AL,20
OUT 82,AL
MOV AL,FFH
OUT 83,AL
MOV AL,40H
OUT 83H,AL
MOV AL,52H
OUT 88H,AL
 8259A- Programmable Interrupt Controller (PIC)

It is a tool for managing the interrupt requests

8259 is a very flexible peripheral controller
chip:
PIC can deal with up to 64 interrupt inputs
8259A Block Diagram
Interrupt Sequence in an 8086 system
Example of two cascaded PICs
Initialization sequence
ICW2 is used to tell 8259A the Interrupt type Number in response to interrupt signal
ICW4 need to send when we are using 8086
 Operational Command Word

Used to Unmask any IR

For eg; IR2 & IR3, OCW1 is 1111 0011
 o

OCW2 is used to reset the In Service Register

Programming the 8259A
 Priority IR0 Highest and IR7 Lowest
Bottom Priority : If IR5 is bottom Priority then
IR5 will have least priority followed by IR4
HIGHER priority
Automatic rotation : round robin fashion
 8259A in single level triggered mode interval
4, non-buffered, no special fully nested mode.