ASIC design from

Design Compiler

PrimeTime
Timing performance
or
and violation report

Layout Verilog from

IC Compiler
Rise/Fall Time

Design
Constraints
Gate delay
set library path read the design link library and the
set search_path read_verilog design
set link_path link

add design add constant value report

constraints to input port (for report_constraint
read_sdc timing simulation) report_timing
set_case_analysis