Multipliers

Integer Multipliers
1
A
B
X P
Multipliers
• A must have circuit in most DSP applications
• A variety of multipliers exists that can be chosen
based on their performance
• Serial, Serial/Parallel,Shift and Add, Array, Booth,
Wallace Tree,….
2
A
B
X P
reset
en
reset
en
converter RA
16x16 Converter
multiplier RC
reset
en
converter RB
3
A
B
X P
Multiplication Algorithm
X= Xn-1 Xn-2 ………..……X0 Multiplicand
Y=Yn-1 Yn-2……………….Y0 Multiplier
Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0

Yn-1X1 Yn-2X1 Yn-3X1 …… Y1X1 Y0X1
Yn-1X2 Yn-2X2 Yn-3X2 …… Y1X2 Y0X2
… … … …
…. …. …. …. ….
Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2

Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 …… Y1Xn-1 Y0Xn-1
-----------------------------------------------------------------------------------------------------------------------------------------
P2n-1 P2n-2 P2n-3 P2 P1 P0
4
1. Multiplication Algorithms
Implementation of multiplication of binary numbers boils down to how to do the additions.
Consider the two 8 bit numbers A and B to generate the 16 bit product P. First generate the 64
partial Products and then add them up.
5
A
B
X P
Multiplier Design
Storage
R R
E E
G G
MU
I ( Multiplier Unit) O
N U
T
Control Unit
6
X: x3x2x1x0 Y:y 3y2y1y0
Serial Multiplier Input Sequence for G1:
A
B
X P
00x3x2x1x00 x3x2x1x0 0x3x2x1x0 0x3x2x1x0
00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0
Reset:010000100001000010000
0 d 1-bit q
Reset=0 G2 REG
CLK
1
0 0
x0y0
+ 0 0 0 0
x0 0
y0 G1 x0y0
Serial Register
CLK CLK/(N+1)
Slide 1
7
Si: the ith bit of the final result X: x3x2x1x0 Y:y 3y2y1y0
Input Sequence for G1:
Reset:010000100001000010000
0 d 1-bit q
Reset=0 G2 REG
CLK
1
0 0
x1y0
+ S0 0 0 0
x1 0
y0 G1 x1y0
Serial Register
CLK CLK/(N+1)
Slide 2
8
Reset:010000100001000010000
0 d 1-bit q
Reset=0 G2 REG
CLK
1
0 0
x2y0
+ x1y0 S0 0 0
x2 0
y0 G1 x2y0
Serial Register
CLK CLK/(N+1)
Slide 3
9
Reset:010000100001000010000
0 d 1-bit q
Reset=0 G2 REG
CLK
1
0 0
x3y0
+ x2y0 x1y0 S0 0
x3 0
y0 G1 x3y0
Serial Register
CLK CLK/(N+1)
Slide 4
10
Reset:010000100001000010000
S0 d 1-bit q
Reset=1 G2 REG
0 CLK
0 0
0
+ x3y0 x2y0 x1y0 S0
0 0
0 G1 0
Serial Register
CLK CLK/(N+1)
Slide 5
11
Ci: the only carry from column i Input Sequence for G1:
Reset:010000100001000010000
x1y0 d 1-bit q
Reset=0 G2 REG
1 CLK
x1y0
C1
S1
+ 0 x3y0 x2y0 x1y0 S0
x0 0
G1 x0y1
y1
Serial Register
CLK CLK/(N+1)
Slide 6
12
Sij: the jth partial sum for column i
Cij: the jth partial carry from column i
Reset:010000100001000010000
x2y0 d 1-bit q
Reset=0 G2 REG
1 CLK
x2y0
C20
S20
+ S1 0 x3y0 x2y0 S0
x1 C1
G1 x1y1
y1
Serial Register
CLK CLK/(N+1)
Slide 7
13
Reset:010000100001000010000
x3y0 d 1-bit q
Reset=0 G2 REG
1 CLK
x3y0
C30
S30
+ S20 S1 0 x3y0 S0
x2 C20
G1 x2y1
y1
Serial Register
CLK CLK/(N+1)
Slide 8
14
Reset:010000100001000010000
0 d 1-bit q
Reset=0 G2 REG
1 CLK
0
C40
S40
+ S30 S20 S1 0 S0
x3 C30
G1 x3y1
y1
Serial Register
CLK CLK/(N+1)
Slide 9
15
Reset:010000100001000010000
S1 d 1-bit q
Reset=1 G2 REG
0 CLK
0
C50=0
S50
+ S40 S30 S20 S1 S0
0 C40
G1 0
0
Serial Register
CLK CLK/(N+1)
Slide 10
16
Reset:010000100001000010000
S20 d 1-bit q
Reset=0 G2 REG
1 CLK
S20
C21
S2
+ 0
S50 S40 S30 S20 S1 S0
x0
G1 x0y2
y2
Serial Register
CLK CLK/(N+1)
Slide 11
17
Reset:010000100001000010000
S30 d 1-bit q
Reset=0 G2 REG
1 CLK
S30
C31
S31
+ C21
S2 S50 S40 S30 S1 S0
x1
G1 x1y2
y2
Serial Register
CLK CLK/(N+1)
Slide 12
18
Reset:010000100001000010000
S40 d 1-bit q
Reset=0 G2 REG
1 CLK
S40
C41
S41
+ C31
S31 S2 S50 S40 S1 S0
x2
G1 x2y2
y2
Serial Register
CLK CLK/(N+1)
Slide 13
19
Reset:010000100001000010000
S50 d 1-bit q
Reset=0 G2 REG
1 CLK
S50
C51
S51
+ C41
S41 S31 S2 S50 S1 S0
x3
G1 x3y2
y2
Serial Register
CLK CLK/(N+1)
Slide 14
20
Reset:010000100001000010000
S2 d 1-bit q
Reset=1 G2 REG
0 CLK
0
C60=0
S60
+ C51
S51 S41 S31 S2 S1 S0
0
G1 0
0
Serial Register
CLK CLK/(N+1)
Slide 15
21
Reset:010000100001000010000
S31 d 1-bit q
Reset=0 G2 REG
1 CLK
S31
C32
S3
+ 0
S60 S51 S41 S31 S2 S1 S0
x0
G1 x0y3
y3
Serial Register
CLK CLK/(N+1)
Slide 16
22
Reset:010000100001000010000
S41 d 1-bit q
Reset=0 G2 REG
1 CLK
S41
C42
S4
+ C32
S3 S60 S51 S41 S2 S1 S0
x1
G1 x1y3
y3
Serial Register
CLK CLK/(N+1)
Slide 17
23
Reset:010000100001000010000
S51 d 1-bit q
Reset=0 G2 REG
1 CLK
S51
C52
S5
+ C42
S4 S3 S60 S51 S2 S1 S0
x2
G1 x2y3
y3
Serial Register
CLK CLK/(N+1)
Slide 18
24
Reset:010000100001000010000
S60 d 1-bit q
Reset=0 G2 REG
1 CLK
S60
C61
S6
+ C52
S5 S4 S3 S60 S2 S1 S0
x3
G1 x3y3
y3
Serial Register
CLK CLK/(N+1)
Slide 19
25
Reset:010000100001000010000
S3 d 1-bit q
Reset=1 G2 REG
0 CLK
S7
+ C61
S6 S5 S4 S3 S2 S1 S0
0
G1 0
0
Serial Register
CLK CLK/(N+1)
Slide 20
26
Reset:010000100001000010000
d 1-bit q
Reset=0 G2 REG
1 CLK
+ 0
S7 S6 S5 S4 S3 S2 S1 S0
0
G1 0
0
Serial Register
CLK CLK/(N+1)
Slide 21
27
Reset:010000100001000010000
d 1-bit q
Reset=0 G2 REG
1 CLK
+ 0
S7 S6 S5 S4 S3 S2 S1 S0
0
G1 0
0
Serial Register
CLK CLK/(N+1)
Slide 21
28
Si: the ith bit of the final result
A
B
X P
Serial / Parallel
Multiplier
y0 y1 y2 y3
x0
D D D
0 0 0
0 0 0
S0 S0 S0
+ + S0
+ S0
D 0 D 0 D 0
Slide 1
29
Ci: the only carry from column i A
B
X P
y0 y1 y2 y3
x1 x0
D D D
0 0
x0y1 0 0
x1y0 S1 S1 S1
+ + + S1 S0
C1
D 0 D 0 D 0
Slide 2
30
Ci: the only carry from column i
A
B
X P
y0 y1 y2 y3
x2 x1 x0
D D D
0
x1y1 x0y2 0
x2y0 S20 S2 S2
+ + + S2 S1 S0
C20 C21
D C1 D 0 D 0
Slide 3
31
Sij: the jth partial sum for column i B

X P
y0 y1 y2 y3
x3 x2 x1
D D D
x0
x2y1 x1y2 x0y3

x3y0 S30 S31 S3
+ + + S3 S2 S1 S0
C30 C31 C32
D C20
D C21
D 0
Slide 4
32
Sij: the jth partial sum for column i B

X P
y0 y1 y2 y3
0 x3 x2 x1
D D D
x3y1 x2y2 x1y3

0 S40 S41 S4
+ + + S4 S3 S2 S1 S0
C40 C41 C42
D C30
D C31
D C32
Slide 5
33
A
S ij: the jth partial sum for column i B

X P
y0 y1 y2 y3
x3 x2
D D D
0 0
0 x3y2 x2y3
0 C40 S51 S5
+ + + S5 S4 S3 S2 S1 S0
0 C50 C51
D C40
D C41
D C42
Slide 6
34
A
S ij: the jth partial sum for column i B

X P
y0 y1 y2 y3
x3
D D D
0 0 0
0 0 x3y3
0 0 C50 S6
+ + + S6 S5 S4 S3 S2 S1 S0
0 0 C6
D 0 D C50
D C51
Slide 7
35
A
B
X P
y0 y1 y2 y3
0
D D D
0 0 0
0 0 0
0 0 0 S7
+ + + S7 S6 S5 S4 S3 S2 S1 S0
0 0 0
D 0 D 0
D C6
Slide 8
36
Shift AND Add Multiplier A
INPUT Ain (7 downto 0) B

X P
REGA
MUX
8 bit Adder INPUT Bin (7 downto 0)
REGC REGB
Result (15 downto 8) Result (7 downto 0)

CLOCK
37
A
B
X P Synchronous Shift and Add Multiplier
controller
 Multiplication process:
 5 states: Idle, Init, Test, Add, and Shift&Count.
 Idle: Starts by receiving the Start signal;
 Init: Multiplicand and multiplier are loaded into a load
register and a shift register, respectively;
 Test: The LSB in the shift register which contains the
multiplier is tested to decide the next state;
38
A
B
X P
Synchronous Shift and Add Multiplier

ControllerDesign
 Add: If LSB is ‘1’, then next state is to add the new partial product to the
accumulation result, and the state machine transits to shift&count state ;
 Shift&Count: If LSB is ‘0’, then the two shift register shift their contains
one bit right, and the counter counts up by one step. After that, the state
machine transits back to test state;
 When the counter reaches to N , a Stop signal is asserted and the state
machine goes to the idle state;
 Idle: In the idle state, a Done signal is asserted to indicate the end of
multiplication.
39
n-bit Multiplier:
Q0=1: Multiplicand is added to register A; the result is stored in register A; registers C, A, Q are shifted to the right
one bit
Q0=0: Registers C, A, Q are shifted to the right one bit
Multiplicand
Add Shift and Add

n-bit Adder
Control Logic
Shift Right
C An-1 An ... A1 A0 Qn-1 Qn ... Q1 Q0
Multiplier
Slide 1
40
Example: 4-bit Multiplier
A
Initial Values
B
X P
Multiplicand
1 0 1 1
Add Shift and Add

4-bit Adder
Control Logic
Shift Right
0 0 0 0 0 1 1 0 1
Multiplier
Slide 2
41
First Cycle--Add A
B
X P
Multiplicand
1 0 1 1
Add=1 Shift and Add

4-bit Adder
Control Logic
Shift Right=0
0 1 0 1 1 1 1 0 1
Multiplier
Slide 3
42
A
First Cycle--Shift
B
X P
Multiplicand
1 0 1 1
Add=0 Shift and Add

4-bit Adder
Control Logic
Shift Right=1
0 0 1 0 1 1 1 1 0
Multiplier
Slide 4
43
Second Cycle--Shift A
B
X P
Multiplicand
1 0 1 1
Add=0 Shift and Add

4-bit Adder
Control Logic
Shift Right=1
0 0 0 1 0 1 1 1 1
Multiplier
Slide 5
44
A
Third Cycle--Add
B
X P
Multiplicand
1 0 1 1
Add=1 Shift and Add

4-bit Adder
Control Logic
Shift Right=0
0 1 1 0 1 1 1 1 1
Multiplier
Slide 6
45
Third Cycle--Shift A
B
X P
Multiplicand
1 0 1 1
Add=0 Shift and Add

4-bit Adder
Control Logic
Shift Right=1
0 0 1 1 0 1 1 1 1
Multiplier
Slide 7
46
Fourth Cycle--Add A
B
X P
Multiplicand
1 0 1 1
Add=1 Shift and Add

4-bit Adder
Control Logic
Shift Right=0
1 0 0 0 1 1 1 1 1
Multiplier
Slide 8
47
Fourth Cycle--Shift A
B
X P
Multiplicand
1 0 1 1
Add=0 Shift and Add

4-bit Adder
Control Logic
Shift Right=1
0 1 0 0 0 1 1 1 1
Multiplier
Slide 9
48
A
B
X P
4*4 Synchronous Shift and Add Multiplier Design
Layout Design
Floor plan of the 4*4 Synchronous

Shift and Add Multiplier
49
A
B
X P
Comparison between Synchronous and Asynchronous

Approaches
.
50
A
Example : (simulated by Ovais Ahmed)
B
X P
Multiplicand = 100010012 = 8916

Multiplier = 101010112 = AB16
Expected Result = 1011011100000112 =5B8316
51
A
B
X P
Array Multiplier
 Regular structure based on add and shift algorithm.
 Addition is mainly done by carry save algorithm.
 Sign bit extension results in a higher capacitive load and

slows down the speed of the circuit.
52
A
Addition with CLA
B
X P
a3 a2 a1 a0
b0
A = a3a2a1a0
B = b3b2b1b0
a3 a2 a1 a0
b1
Ci
Cout Four-bit Adder 0
n
a3 a2 a1 a0
b2
Cout Four-bit Adder Cin 0
a3 a2 a1 a0
b3
Cout Four-bit Adder Cin 0
53
Product (A*B)
A
B
X P
Array Multiplier with CSA

A3 A2 A1 A0
P03 P12 0 P02 P11 0 P01 P10 0 P00
**Pij =Ai Bj
F.A F.A F.A

Total of 16 Aj Bi B0
gates
B1 Ci Si Ci Si Ci Si
B2
0i3 P13 P22 P21 P20
0 j3 B3
F.A F.A F.A

Pij Ci Si Ci Si Ci Si
P23 P32 P31 P30
F.A F.A F.A
Ci Si Ci Si Ci Si
P33 0
F.A F.A F.A
Ci Si Ci Si Ci Si
54
R7 R6 R5 R4 R2 R1 R0
R3
A
B
X P
Critical Path with Array Multipliers
FA FA FA HA
FA FA FA HA
FA FA FA HA
Two of the possible paths for the Ripple-Carry based 4*4 Multiplier
Area = (N*N) AND Gate + (N-1)N Full-Adder
Delay = τ HA + (2N-1) τ FA
55
A
B
X P
56
A
B
X
P9
P
x4y4
P8
+
x3y4
P7
+
+
x4y3
x2y4
P6
+
+
+
x3y3
x4y2
x1y4
x2y3
x3y2
P5
+
+
+
+
x4y1
x0y4
x1y3
x2y2
P4
+
+
+
+
x3y1
x4y0
Wallace Tree
x0y3
x1y2
x2y1
P3
+
+
+
x3y0
x0y2
x1y1
P2
+
+
P1 x2y0
x0y1
+
x1y0
x0y0
P0
57
A
B
X P
Array Multiplier + Wallace Tree
58
A
B
X P
Baugh-Wooley Algorithm
Convert negative partial products to positive representation
• No sign-extension required
k 2 k 2
X * Y  ( xk 1 * 2 k 1
  xi * 2 ) * ( yk 1 * 2
i k 1
  yi * 2 i )
i 0 i 0
k 2 k 2 k 2 k 2
 ( xk 1 * yk 1 * 2 2 k 2
  xi y j * 2 )   xk 1 yi * 2
i j k 1i
  yk 1 xi * 2 k 1i
i 0 j 0 i 0 i 0
3/10/2018 59 59
A
X P examples of 5-by-5 Baugh-Wooley

B
0 0 a2b0 0 a1b0 0 a0b0
a4b0' a3b0
a3b1 a2b1 a1b1

FA FA FA FA a0b1
a4b1'
a3b2 a2b2 a1b2 a0b2

FA FA FA FA
a4b2'
a3b3 a2b3 a1b3 a0b3

FA FA FA FA
a4b3'
a4' b4'
a4b4
1 FA FA a3'b4 FA a2'b4 FA a1'b4 FA a0'b4
a4
FA FA FA FA FA FA b4
P9 P8 P7 P6 P5 P4 P3 P2 P1
P0
The schematic logic circuit diagram of a 5-by-5 Baugh-Wooley two’s complement array multiplier
3/10/2018 60
A
Squarer using Baugh-Wooley Algorithm
B
X P
a7 a6 a5 a4 a3 a2 a1 a0
* a7 a6 a5 a4 a3 a2 a1 a0
-------- ------- -------- ------- -------- -------- ------- -------- -------- ------- -------- ------- -------- ------- --------
----- ------ ----- ------ ----- ----- ------ ----- ----- ------ ----- ------ ----- ------ -----
a5*a a3*a a1*a

a7*a0 a6*a0 0 a4*a0 0 a2*a0 0 a0*a0
a7*a a4*a a2*a a0*a

1 a6*a1 a5*a1 1 a3*a1 1 a1*a1 1
a6*a a3*a a1*a

a7*a2 2 a5*a2 a4*a2 2 a2*a2 2 a0*a2
a5*a a2*a a0*a

a7*a3 a6*a3 3 a4*a3 a3*a3 3 a1*a3 3
a7*a a4*a a1*a

4 a6*a4 a5*a4 4 a3*a4 a2*a4 4 a0*a4
a6*a a3*a a0*a

a7*a5 5 a5*a5 a4*a5 5 a2*a5 a1*a5 5
a7*a a5*a a2*a

6 a6*a6 6 a4*a6 a3*a6 6 a1*a6 a0*a6
a6*a a4*a a1*a

a7*a7 7 a5*a7 7 a3*a7 a2*a7 7 a0*a7
-------- ------- -------- ------- -------- -------- ------- -------- -------- ------- -------- ------- -------- ------- -------- 61
----- ------ ----- ------ ----- ----- ------ ----- ----- ------ ----- ------ ----- ------ -----
a7*a a7*a a7*a a4*a a2*a

A
B
X P
Example of an 8bit squarer
a6a2 a6a1 a5a1 a4a1 a3a1 a2a1 a2a0 a1a0 ‘0’ a0

a7a1 a5a3 a7a0 a5a2 a6a0 a4a2 a5a0 a3a2 a4a0 a3a0 a2 ‘0’ a1
‘0’
a6a3
a7a2 a5a4
a3a4 a3
‘0’
‘0’
a6a5 a6a4
a7a4 a6 a7a3
a5 a4
‘0’
a7
a7a6 a7a5
‘0’
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
62
A
B
X P
Array Multiplier
32bits by 32bits multiplier
63
A
Booth (Radix-4) Multiplier B

X P
 Radix-4 (3 bit recoding) reduces number of partial products to be

added by half.
 Great saving in area and increased speed.
A = -an-12n-1 + an-22n-2 + an-32n-3 + …. + a12 + a0

B = -bn-12n-1 + bn-22n-2 + bn-32n-3 + …. + b12 + b0
· Base 4 redundant sign digit representation of B is

(n/2) - 1
B=  22i Ki
i=0
64
  Ki is calculated by following equation
Ki = -2b2i+1 + b2i + b2i-1 i = 0,1,2,….(n-2)/2
 3 bits of Multiplier B, b2i+1, b2i, b2i-1, are examined and

corresponding Ki is calculated.
 B is always appended on the right with zero (b-1 = 0), and n is

always even (B is sign extended if needed).
 The product AB is then obtained by adding n/2 partial products.

(n/2) - 1
AB = P =  22i Ki A
i=0
65
A
B
X P
Booth Algorithm
Decoding of multiplier to generate signals for hardware use
Xi+1 Xi Xi-1 OP NEG ZERO TWO
0 0 0 0 0 1 0
1 0 0 2 1 0 1
0 1 0 1 0 0 0
1 1 0 1 1 0 0
0 0 1 1 0 0 0
1 0 1 1 1 0 0
0 1 1 2 0 0 1
1 1 1 0 1 1 0
66
A
B
X P
Booth Algorithm
A Booth recoded multiplier examines
Three bits of the multiplicand at a time
It determine whether to add zero, 1, -1, 2, or -2 of that rank of
the multiplicand.
The operation to be performed is based on the current two bits
of the multiplicand and the previous bit
Xi+1 X Xi-1 Zi/2
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 2
1 0 0 -2
1 0 1 -1
1 1 0 -1
1 1 1 0 67
BIT M is
multiplied
OPERATION
21 20 2-1 by
Xi Xi+1 Xi+2
0 0 0 add zero (no string) +0
0 0 1 add multipleic (end of string) +X
0 1 0 add multiplic. (a string) +X
0 1 1 add twice the mul. (end of string) +2X
1 0 0 sub. twice the m. (beg. of string) -2X
1 0 1 sub. the m. (-2X and +X) -X
1 1 0 sub . the m. (beg. of string) -X
1 1 1 sub. zero (center of string) -0
68
A
B
X P
Booth Algorithm- dot notation
Multiplicand A = ● ●●●
Multiplier B= (●●)(●●)
Partial product bits ● ● ● ● (B1B0)2A40

Partial product bits ● ●●● (B3B2)A41
Product P= ● ●●●● ●●●
69
A
Example B
X P
The following example is used to show how the calculation is done properly.
Added to
Multiplicand X = 000011 the
multiplier
Multiplier Y = 011101 0 1 1 1 0 1 0
After booth decoding, Y is decoded as to multiply X by +2, -1, +1 separately, then shift the partial
product two bits and add them together.
X* +1 000000000011
X* -1 1111111101
X* +2 00000110
--------------------------------------------
000001010111
70
A
B
X P
Sign Extension
71
A
B
X P
Sign extension
 Traditional sign-extension scheme
• Segment the input operands based on the size of
embedded blocks
• Multiply the segmented inputs and extend the sign bit of
each partial products
• Sum all partial products
Segmented input
× operands
Sign extension
partial
products
+
Sign Final result
3/10/2018 Concordia VLSI Lab 72 72
A
B
X P
Booth Algorithm-Example 1
Example 1:
000011 (+3)
011101 0 (+29)
+2 -1 +1
000000000011
1111111101
00000110
1 000001010111 (+87)
73
A
B
X P
Booth Algorithm Example 2
Notice sign
extensions 111101 (-3)
011101 0 (+29)
+2 -1 +1
2s complement of 111111111101
0000000011
multiplicand
11111010
1 111110101001 (-87)
74
A
B
X P
Booth Algorithm-Example 3
Notice the sign

extensions 111101 (-3)
100011 0 (-29)
-2 +1 -1
Shifted 2s 000000000011
1111111101
complement
00000110
1 000001010111 (+87) 75
A
B
X P
Comparison of Booth and parallel

multiplier shift and Add
76
Template to reduce sign extensions for Booth
Algorithm
Please note that each operand is 17 bit ie. the 17th bit is the sign bit. Also
negative numbers are entered as 1’s complement, this is why you need to
add the S in the right hand side of the diagram. If you use 2’complement
then the S’s on right side of the diagram can be removed
77
A
B
X P
Comparison of Template and the sign

extension
A A
B B
S1 S1 S1 S1 S1 S1 S1 S1 S1 S1
1 S2 S2 S2 S2 S2 S2
S3 S3 S3 S3
S4
P P
Sign template Sign extension
78
3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 1 0
3 2
2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
A A
S S S A A A A A A A A A A A A A A A
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A A
1 S A A A A A A A A A A A A A A A
1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 S A A A A A A A A A A A A A A A A A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Partial
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Product
matrix
1 S A A A A A A A A A A A A A A A A A generated for
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
a 16 * 16 bit
multiplication
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 ,
Using booth
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
and the
template
A A A A A A A A A A A A A A A A A A given in
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
previous slide
S A A A A A A A A A A A A A A A A
8
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
79
A
B
X P
Example of using the template
25 * - 35 with -35 as the multiplier. Using 8 bit representation
Using the Template 25 * -35

Sign bit
00011001
Add SS 110111010
Add inverted S
Add Inverted sign and add 1
10000011001 * 1
Add Inverted sign bit 1011100111 * -1
100110010 * 2
No sign bit 1100111 * -1
11110010010101
This is a –ve number. Convert it
00001101101011
512 256 64 32 8 2 1 = 875
80

Multipliers

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Multipliers

Uploaded by

Copyright:

Available Formats

Integer Multipliers

Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0

Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2

P2n-1 P2n-2 P2n-3 P2 P1 P0

Sij: the jth partial sum for column i B

Cij: the jth partial carry from column i

x2y1 x1y2 x0y3

C30 C31 C32

Sij: the jth partial sum for column i B

Cij: the jth partial carry from column i

x3y1 x2y2 x1y3

C40 C41 C42

S ij: the jth partial sum for column i B

Cij: the jth partial carry from column i

S ij: the jth partial sum for column i B

Cij: the jth partial carry from column i

INPUT Ain (7 downto 0) B

8 bit Adder INPUT Bin (7 downto 0)

Result (15 downto 8) Result (7 downto 0)

Synchronous Shift and Add Multiplier

Add Shift and Add

C An-1 An ... A1 A0 Qn-1 Qn ... Q1 Q0

Add Shift and Add

Add=1 Shift and Add

Add=0 Shift and Add

Add=0 Shift and Add

Add=1 Shift and Add

Add=0 Shift and Add

Add=1 Shift and Add

Add=0 Shift and Add

Floor plan of the 4*4 Synchronous

Comparison between Synchronous and Asynchronous

Multiplicand = 100010012 = 8916

 Regular structure based on add and shift algorithm.

 Addition is mainly done by carry save algorithm.

 Sign bit extension results in a higher capacitive load and

Cout Four-bit Adder Cin 0

Cout Four-bit Adder Cin 0

Array Multiplier with CSA

F.A F.A F.A

F.A F.A F.A

P23 P32 P31 P30

F.A F.A F.A

F.A F.A F.A

Array Multiplier + Wallace Tree

X P examples of 5-by-5 Baugh-Wooley

a3b1 a2b1 a1b1

a3b2 a2b2 a1b2 a0b2

a3b3 a2b3 a1b3 a0b3

a5*a a3*a a1*a

a7*a a4*a a2*a a0*a

a6*a a3*a a1*a

a5*a a2*a a0*a

a7*a a4*a a1*a

a6*a a3*a a0*a

a7*a a5*a a2*a

a6*a a4*a a1*a

a7*a a7*a a7*a a4*a a2*a

Example of an 8bit squarer

a6a2 a6a1 a5a1 a4a1 a3a1 a2a1 a2a0 a1a0 ‘0’ a0

S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Booth (Radix-4) Multiplier B

 Radix-4 (3 bit recoding) reduces number of partial products to be

a5a a3a a1*a

a7a a4a a2a a0a

a6a a3a a1*a

a5a a2a a0*a

a7a a4a a1*a

a6a a3a a0*a

a7a a5a a2*a

a6a a4a a1*a

a7a a7a a7a a4a a2*a