Gotchas

Queries
Enable flop
Clock gating circuit
How to fix setup and hold violations?

To address setup time violations, you can:

Use larger/stronger cells to drive paths with high capacitance, which can reduce the
time needed to transition on sluggish net.
Adjust the skew of the clock to the start or endpoint of the path which is violating.
(time borrowing).
Move gates around to make the total distance between different cells in the violating
path smaller (less capacitance to drive = faster transitions)
Insert retiming flops on the path, if the design will allow for it (try to do an operation
in two clock cycles instead of one)
Reduce the overall clock frequency.
For hold time violations:
Skew the clock to the start/endpoint (reverse of how to fix setup) to make the
endpoint clock arrive earlier.
Insert cells along the path to increase the propogation time (insert chains of buffers)
Reduce the drive strength of cells on the path to make the transition time increase.
Setup violation in feedback path of single FF
Suppose I am having a design in which the Q output of an FF is fed
back to the D input of the same FF through some combinational
logics. If I am having set up violations in this situation, how can I
fix it? Insteda of having set up violations, if I am having hold
violations, how can I fix them?? What if I have both set up and
hold violations??

Same as previous slide. one caveat of these scenarios is that

capture/launch clock are always the same, so you can't leverage
useful skew in any way.
Power
Three power dissipating sources:
1. Activity of logic circuits
2. Leakage of logic circuits
3. Analog and IO buffers – not activity dependent not leakage
Difference between –fall and –clock_fall
Hold
Negative hold time of flops

Multicycle path and metastability => needs dynamic simulation?

use enable FF
STA of latches.
-Check this!

http://chipverification.blogspot.com/2008/05/clock-
dividers.html

https://electronics.stackexchange.com/questions/39709/using-
both-edges-of-a-clock
Timing arcs
Input delay timing arc:
From clk to data
Output delay timing arc:
From data to clock

Max analysis: Max data path and min clock path

Min analysis : Min data path and max clock path.
Negative gate delay
Propagation delay: output reaching 50% - input reaching 50%

Negative delay is a relative concept.

When output 50% reaches faster than input 50%

It can happen when:

1. A high drive strength transistor
2. Slow transition at the input
3. Small load at the output
Negative net delay
A net has only passive parasitic – parasitic resistances and capacitances. So it will only
dissipate, hence not possible to have negative propagation delay.

When crosstalk is there, output can read 50% before input. This can cause a negative
propagation delay.

In FPGAs, there are routing switches. These are simply gates. Hence, in FPGA timing
reports we can see negative delays.
Latch timing
Timing arcs
Three arcs:
1. Data -> Out: When enable is asserted, output follows data pin.
2. Enable -> Out: When data is stable, but when enable gets asserted, output changes wrt enable.
3. Enable -> Data: Timing check arc. When data toggles near closing edge of enable, there is confusion
which data will be latched. So we impose setup and hold checks, and this becomes setup and hold
arcs.
 Conventions
For delay arcs
Max and min after clock/related +ve
Max and min before clock/related –ve.

Max and min value after clock -ve

Max and min value before clock +ve
Need a logic
Need a common logic to find which edges
are used for max and min analysis:
relationship between them.

Read: Two hold check