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Elprince - Performance Evaluation Study For HiperLan WLAN Protocol-FINAL
Elprince - Performance Evaluation Study For HiperLan WLAN Protocol-FINAL
Omar A. Elprince
Student#220510
Agenda
What is HIPERLAN?
Origin of HIPERLAN
HIPERLAN MAC
Mechanism
HIPERLAN Family
Features of HiperLAN/2
MAC Frame Structure
Transport Channels
The Channel Access Mechanism
Signaling and Control
Error Control
Simulation Results
What is HIPERLAN?
Talk
Talk
Station 2 Listen
Talk
stops
Station 3 Listen
Talk
stops
Station 4 Listen
stops
Time
HIPERLAN MAC (Cont’d)
Phases
Prioritization Phase
1-5 slots of 168bits (talk)
Contentions Phase
Elimination - 0-12 slots of 212bits (talk),
1 slot of 256bits (listen), prob(talk-listen) = 0.5
Yield - 0-9 slots of 168bits (listen), prob(n) = 0.1
Tx to Rx turn around time 6s
256 contenders, 3.5% collision probability
Total of 0-5152bits (0-219s) MAC header
HIPERLAN MAC (Cont’d)
Performance:
Acknowledge:
Based on Selective Repeat (SR)
Provides reliable transmission
Repetition
Reliable Retransmission by repeating the DLC PDUs
Transmitter arbitrarily retransmits the PDUs, but the receivers accepts
only in a sequential order
Unacknowledge
Unreliable Transmission
Transmitter sends the PDUs in increased sequential order, and the
receiver will deliver the received ones to the Convergence Layer (CL)
Centralized/Direct Mode used by
HiperLAN/2
DEMO
Hiperlan Performance Simulation
(Cont’d)
%Network throughput vs %load
80
%Network Throughput
70
60
50 25 users throughput
40 8 users throughput
30 2 users throughput
20
10
0
0
11
16
17
25
59
63
73
74
94
%Load
Hiperlan Performance Simulation
(Cont’d)
MAC Delay
1.2
Average MAC delay
1
0.8 delay of 2 nodes
0.6 delay of 8 nodes
0.4 delay of 25 nodes
0.2
0
49 52 52 58 72 83 89 91 93 10 0
% Load