COMPUTER ARCHITECTURE

PRESENTATION
MULTIPROCESSORS
• What is Processor?
A processor is an
integrated electronic circuit that performs
the calculations that run a computer. A
processor performs arithmetical, logical,
input/output (I/O) and other basic
instructions that are passed from an
operating system (OS). Most other
processes are dependent on the
operations of a processor.
 MULTIPROCESSOR OPERATING SYSTEM

• Multiprocessor Operating System

refers to the use of two or more
central processing units (CPU) within
a single computer system. These
multiple CPUs are in a close
communication sharing the computer
bus, memory and other peripheral
devices. These systems are referred
as tightly coupled systems.
CHARACTERISTICS
• If a fault causes one processor to fail , another processor can be assigned to perform the
functions of disabled processor.
• The benefit derived from a multiprocessor organization is an improved system performance.
• Multiprocessing improves the reliability of the system so that a failure in one part has a
limited effect on the rest of the system
• Multiprocessors are classified as multiple instruction stream multiple data stream(MIMD)
systems.
• Multiprocessor systems are cheaper than single processor systems in the long run because they
share the data storage, peripheral devices, power supplies etc. If there are multiple processes
that share data, it is better to schedule them on multiprocessor systems with shared data than
have different computer systems with multiple copies of the data.
INTERCONNECTION STRUCTURES

• A Multiprocessor consist of a set of components like CPU,

memory ,I/O processors etc. that communicate with each
other.
• The collection of path connecting the various modules is
called the interconnection structure.
BUS ORIENTED SYSTEM

• A shared bus is used to connect various processors & memory unit.

• A large number of processors can communicate with each other as well as with
global shared memory one shared bus.
• In shared bus organization, contention occur at shared memory & shared bus, so in
order to reduce the contention ,cache memory can be associated with each processor.
• In shared bus there is only single bus and only one processor can transmit data on
bus, at that time other processor will either do local task wait for bus.
• Therefore for speed of transmission limited to single path.
 Overcome limitation of time shared bus multiple bus system is used.
 It consist of hierarchy of buses connecting various system & sub systems components
in a computer.
 VARIOUS BUSES
 Local buses
 System buses
 Expansion buses
• LIMITATION:
System bus can be accessed by one processor at a time that means only one
processor can communicate with memory .
INTERPROCESSOR ARBITRATION

• Computer system needs buses to facilitate the transfer of information between

its various components. System bus connects CPU, IOP & memory(main
components of computer). Only one of CPU, IO & memory can be granted to
use the bus at a time. Hence, an appropriate priority resolving mechanism is
required to decide which processor should get control of bus. Arbitration
mechanism is needed to handle multiple requests for bus. Arbitration
procedure services all processor requests on the basis of established priorities.
ARBITRATION TECHNIQUES
Static arbitration technique
Dynamic arbitration technique
 Static arbitration technique:
In static techniques the priorities assigned are fixed.
1. Serial arbitration procedure
2. Parallel arbitration procedure
SERIAL ARBITRATION PROCEDURE:

• It is also called daisy chain arbitration.

It is obtained by daisy chain connection
of bus arbitration circuit. This scheme
got its from the structure for the grant
line which chains through each device
from the highest priority to the lowest
priority. The highest priority device will
pass the grant line to the lower priority
device only if it does not want it. All
devices use the same line for bus
request.
• Parallel Arbitration Procedure:
It uses an external priority encoder and priority
decoder. Each bus arbiter has a bus request
output lines and a bus acknowledge input lines.
Each arbiter enables request line when its
processor is requesting the system bus. The one
with highest priority determine by the output of
the decoder get access to the bus.
• Priority Encoder & Decoder:
• It is used when a set of components (e.g.
processor, memory I/O devices etc) are to share
a common resource (e.g. a bus). Each component
is assigned a certain priority according to its
importance.
DYNAMIC ARBITRATION TECHNIQUE
Priorities of the units can be dynamically changeable while the system is in operation.
The various algorithms used are:
 Time Slice: Fixed length time slice is given sequentially to each processor.
 Polling: In polling the controller is used to generate the addresses for the device.
 LRU: This algorithm gives the highest priority to the requesting device that has not used the
bus for the longest interval.
 FIFO: In FIFO, request are served in order received.
 Rotating Daisy Chain: It is dynamic extension of daisy chain algorithm. In this scheme there is
no control bus and the priority line is connected from the priority out of the last device back to
the priority in of the first device in a closed loop.
INTERPROCESSORS COMMUNICATION

• A Processor can of Two Types

1. Independent Processor
2. Co-Operating Processor
Interprocessor Communication is mechanism which allow
Processors to communicate with each other and Synchronize
their actions.
• Processor can communicate with each in two ways
1. Shared Memory
2. Message Passing
Shared Memory
• Message Passing
1. Direct Message Passing
2. Indirect Message Passing
CACHE COHERENCE