AVR Micro Controller

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 AVR Micro-Controller

 Advanced Virtual RISC

 AVR Micro controllers is Family of
RISC Microcontrollers from Atmel.

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 AVR Micro-Controller

The AVR is a Harvard architecture

CPU.

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 AVR Micro-Controller

A series of 8-bit RISC

microcontrollers from Atmel.
 All AVR microcontrollers share
same instruction set and a basic
CPU (Harvard) architecture.

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 AVR Micro-Controller

 It has 32 8-Bit general purpose

registers.
 Mostly instruction Execute in
Single clock cycle.

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 AVR Micro-Controller

 AVR is a family of 8-bit

microcontrollers with a large range
of variants differing in:
 size of program-memory (flash)
 size of EEPROM memory
 number of I/O pins
 number of on-chip features such as uart and adc
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 AVR Micro-Controller

 Smallest microcontroller is the

ATTiny11 with 1k flash ROM, no RAM
and 6 I/O pins.
Large such as the ATMEGA128 with
128k flash, 4KB RAM, 53 I/O pins
and lots of on-chip features.
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 AVR Architecture
 RISC architecture with CISC
instruction set
 Single cycle execution
 One instruction per external clock
 Low power consumption
 32 working registers
 All registers are directly connected to
ALU
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AVR Architecture

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AVR Block Diagram

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 Addressing modes
 Way of accessing memory
 Register Addressing (32 GPR, 64 I/O)
 Data Addressing (SRAM)
 Program Addressing

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 Register Addressing
 Three modes
 Register Direct, Single Register (R0-R31)
 Register Direct, Two Register (R0-R31)
 I/O Direct Addressing (64 I/O
Registers)

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Register Direct, Single Register

Register File
0
15 4 0
OP d

d
Example:
INC R16
CLR R22

31

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 Register Direct, 2 Register
Register File
0
15 5 4 0
OP r d

Example:
ADD R16, R17 31
CP R22, R5
MOV R0, R1
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 I/O Direct
I/O Memory
0
15 5 4 0
OP n p

Example:
IN R16, PIND
OUT PORTC, R16

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 Data Addressing
 There are five modes
 Direct Data Addressing
 Data Indirect with Displacement (Y or Z)
 Data Indirect (X, Y, or Z)
 Data Indirect with pre-decrement (X, Y,
or Z).
 Data Indirect with post-decrement (X, Y,
or Z) 16
 Data Direct
Data space
$0000

31 19 16
OP p
16 LSBs
15 0

Example:
STS 0x1000, R16

$FFFF

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 Data Indirect
Data space
$0000

X, Y, or Z Register
15 0

Example:
LD R16, Y
ST Z, R16

$FFFF

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Data Indirect w/ Displacement
Data space
$0000

Y or Z Register
15 0

Example:

LDD R16, Y+0x10
STD Z+0x20, R16

15 10 5 0 $FFFF
OP n a

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Data Indirect: Pre-Decrement
Data space
$0000

X, Y or Z Register
15 0
Example:
LD R16, -Z
ST -Z, R16

-1

$FFFF

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Data Indirect: Post-Increment
Data space
$0000

X, Y or Z Register
15 0
Example:
LD R16, Z+
ST Z+, R16

1

$FFFF

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 Program Addressing
 There are five modes
 Program Memory Constant Addressing
 Program Memory Addressing with post-
increment
 Direct Program Addressing
 Indirect Program Addressing
 Relative Program Addressing

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 Program Memory constant
Addressing
Program Memory
$0000

Z Register
15 0

LSB
Example:
LDI ZL, 0x55
LDI ZH, 0x02; Z = 0x0255
LPM R17, Z
SPM Z, R17 $FFFF

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 Program Memory Addressing
with post-increment
Program Memory
$0000

Z Register
15 0

LSB
1 +
Example:
LDI ZL, 0x55
$FFFF
LDI ZH, 0x02; Z = 0x0255
LPM R16, Z+
LPM R17, Z 24
 Direct Program Memory
Addressing
31 16 Program Memory
OP 6 LSB $0000
16 LSB
15 0

21 0
PC

Example:
JMP Address1
RJMP Address2
CALL Function1
RCALL Function2 $FFFF

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 Relative Program Memory
Addressing
Program Memory
$0000

PC
15 0

+
15 12 11 0
OP k

Example: $FFFF
RJMP
RCALL
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 AVR Instruction Set
 Load/store architecture
 At most two operands in each
instruction
 Most instructions are two byte long
 Some instructions are four byte

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 AVR Instruction Set
 Four categories
 Arithmetic and logic instructions
 Program Control instructions
 Data transfer instructions
 Bit and bit test instructions

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 General-purpose Register
AVR
 32 general registers
 Named r0, r1,…,r31
 Broken into two parts with 16 register
each
 Each register is assigned a memory
address in SRAM space

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 General-purpose Register
AVR
 Register r0 and r26 through r31 have
additional function
• R0 is used in the instruction LPM (load
program memory)
• Register x (r27:r26), y (r29:28) &
z(r31:r30) used as a pointer register

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 Cont…
Address
0x00 r0
0x01 r1

.
.
.
0x1A r26 x register low byte
0x1B r27 x register high byte
0x1C r28 y register low byte
0x1D r29 y register high byte
0x1E r30 z register low byte
0x1F r31 z register high byte
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 The Status Register in AVR

 The Status Register (SREG) contains

information about result of the most
recently executed arithmetic
instruction.

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 The Status Register in AVR

 SREG is updated after all AL

operations.
 SREG is not automatically stored
when entering an interrupt routine.

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The Status Register in AVR

I T H S V N Z C

Bit 7 6 5 4 3 2 1 0

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 The Status Register in AVR

 Bit 7 – I: Global Interrupt Enable

 Used to enable & disable interrupt
1: enabled, 0: disabled
 The I-bit is cleared by hardware after an
interrupt occurred & is set by the RETI
instruction.

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 The Status Register in AVR

 Bit 6 – T: Bit Copy Storage

 The Bit Copy instruction BLD (Bit LoaD)
& BST (Bit Store) use the T-bit as a
source & destination.
• BLD – A bit from register file to T
• BST – A bit from T to register file

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 The Status Register in AVR

 Bit 5 – H: Half Carry

 Indicates a carry (carry from bit 4)
 Half carry is useful in BCD arithmetic
 Bit 4 – S: Sign Bit
 Exclusive OR b/n the negative flag N
& the Two’s complement overflow
flag V (S = NV)
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 The Status Register in AVR

 Bit 3 – V: Two’s complement

overflow Flag
 Supports two’s complement arithmetic
 Bit 2 – N: Negative Flag
 The most significant bit of a result

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 The Status Register in AVR

 Bit 1 – Z: Zero Flag

 Indicates a result in an arithmetic or
logic operations
 Bit 0 – C: Carry Flag
 Indicate when there is a carry out of the
most significant bit

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 Data Transfer Instruction

 MOV – Move between registers

 LD/LDI – Load / Load Immediate
 ST/STI – Store / Store Immediate

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 Data Transfer Instruction

 LPM – Load Program Memory

 IN/OUT – In and Out Ports
 PUSH/POP – On and off stack

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 Arithmetic & Logic
Instructions
 add, adc, inc
 sub, sbc, dec
 mul, muls, mulsu
 and, or, eor
 clr, cbr, cp, cpc, cpi, tst
 com, neg
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 Add without carry

 Add the contents of two general purpose

registers (GPRS)
Syntax: add Rd, Rr
Operand: Rd, Rr  {r0, r1,…., r31}
Operation: Rd  Rd + Rr
Flags affected:H, S, V, N, Z, C

Example: add r1, r2 ; Add r2 to r1

add r28, r28 ; Add r28 to itself

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 Add with carry

 Add two GPRs plus a 1 if C = 1

Syntax: adc Rd, Rr

Operand: Rd, Rr  {r0, r1,…., r31}
Operation: Rd  Rd + Rr + C
Flags affected: H, S, V, N, Z, C

Example: add r1, r2 ; Add r2 to r1

adc r3, r4

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 Increment

 Increment the contents of GPRs by

One
Syntax: inc Rd
Operand: Rd  {r0, r1,…., r31}
Operation: Rd  Rd + 1
Flags affected: S, V, N, C
Example:
clr r22 ; clear r22
loop: inc r22 ; Increment r22
cpi r22, $4F ; compare with 4F
brne loop ; branch to loop if not equal
nop 45
 Add constant to 16-bit
register
 ADIW – Add a constant to a 16 bit
register
Example:
ADIW R25:R24, 5

 Not all 32 GPRs can be addressed.

Only R25:R24, R27:R26, R29:R28,
R31:R30
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 Subtract without carry

 Subtract two GPRs

Syntax: sub Rd, Rr

Operand: Rd  {r0, r1,…., r31}
Operation: Rd  Rd – R2
Flags affected: H, S, V, N, Z, C

Example:
sub r13, r12; subtract r12 from r13

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 Subtract with carry

Subtract two GPRs minus the carry

Syntax: sbc Rd, Rr

Operand: Rd  {r0, r1,…., r31}
Operation: Rd  Rd – R2 - C
Flags affected: H, S, V, N, Z, C

Example:
sub r0, r1 ; subtract r1 from r0
sbc r2, r3 ; subtract with carry

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 Subtract a constant

 subi - Subtract a constant from a

single GPR

Example:
subi r16, 5 ; subtract 5 from r16

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 Subtract a constant

 suci - Subtract a constant from a

single GPR minus carry

Example:
suci r16, 5 ; subtract 5 from r16 minus carry

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 Decrement

 Decrement the content of GPRs by one

Syntax: dec Rd
Operand: Rd  {r0, r1,…., r31}
Operation: Rd  Rd - 1
Flags affected: S, V, N, C

Example:
ldi r17,$10 ; Load 10 to r17
loop: add r1,r2 ; add r1 and r2
dec r17 ; decrement r17
brne loop ; branch to loop if not equal
nop
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 Subtract constant to 16-bit
register
 SBIW – Subtract a constant to a 16
bit register
Example:
SBIW R31:R30, 63

 Not all 32 GPRs can be addressed.

Only R25:R24, R27:R26, R29:R28,
R31:R30
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 Unsigned Multiplication

Syntax: mul Rd, Rr

 Operand: Rd, Rr  {r0, r1,…., r31}
 Operation: r1,r0  Rd * Rr
 Flags affected: Z, C
 Example:
mul r6, r7
mov r6, r1
mov r7, r0 53
 Signed Multiplication

Syntax: muls Rd, Rr

 Operand: Rd, Rr  {r0, r1,…., r31}
 Operation: r1,r0  Rd * Rr
 Flags affected: Z, C
 Example:
muls r6, r7
movw r17:r16, r1:r0

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 Signed & unsigned
Multiplication
Syntax: mulsu Rd, Rr
 Operand: Rd, Rr  {r0, r1,…., r31}
 Operation: r1,r0  Rd * Rr
 Flags affected: Z, C
 Example:
muls r6, r7

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 Bitwise AND

 Performs a bit-wise logical AND operation

between two GPRs

Syntax: and Rd, Rr

Operand: Rd, Rr  {r0, r1,…., r31}
Operation: Rd  Rd . Rr
Flags affected: S, V, N, Z

Example:
ldi r2, 0b00110101
ldi r16, 1
and r2, r16
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 Bitwise AND with constant

 ANDI – Performs AND operation b/n a

single GPR and immediate value

Example:
andi r16, 0xF0

Only register R16 – R31 are used

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 Bitwise OR

 Performs a bit-wise logical OR operation

between two GPRs

Syntax: or Rd, Rr
Operand: Rd, Rr  {r0, r1,…., r31}
Operation: Rd  Rd + Rr
Flags affected: S, V, N, Z

Example:
ldi r2, 0b00110101
ldi r16, 1
or r2, r16
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 Bitwise OR with constant

 ANDI – Performs AND operation b/n a

single GPR and immediate value

Example:
ori r18, 0xF0

Only register R16 – R31 are used

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 Bitwise XOR

 Performs a bit-wise logical XOR operation

between two GPRs

Syntax: eor Rd, Rr

Operand: Rd, Rr  {r0, r1,…., r31}
Operation: Rd  Rd  Rr
Flags affected: S, V, N, Z

Example:
eor r4, r4
eor r0, r1
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 1’s Complement

 Performs 1’s complement of a GPR

Example:
ldi r0, 0x4A
com r0

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 2’s Complement

 Performs 2’s complement of a GPR

Example:
ldi r0, 0x4A
neg r0

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 Bit Manipulation

 sbr – same as ori

 cbr – similar to andi but with the k
complement

Example:
ldi r16, $AA ldi r16, $AA
andi r16, $F0 cbr r16, $0F

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 Bit Manipulation

 ser – loads a $FF to a register

- similar to ldi rd, $FF
- r16 – r31 can be used
- Does not modify SREG

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 Bit Manipulation
 clr – loads a $00 to a register and does it
by performing eor to itself
- Does modify flags
 tst – Checks if a register is zero or
negative
- The register is not changed but flags
are modified.

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 Branch Instruction

 RJMP
 Relative jump to an address within +/-
2k.
 Unconditional jump
 JMP
 Absolute jump to an address within 4M
(words/addresses) of program memory.
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 Branch Instruction

 IJMP
 Indirect jump to an address pointed by
the Z.
 Maximum jump = 64k

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 Branch Instruction

 RCALL
 Relative call to an address within +/- 2k

 CALL
 Absolute call to an address within 4M of
program memory

 ICALL
 Indirect call to an address pointed by the Z.

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 Branch Instruction

 RET
 Return from subroutine
 RETI
 Return from interrupt

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 Skip Instruction

 SBRC
 Skip the next instruction if a bit in a
register is 0

Example:
sbcr r0, 4
rcall task
nop
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 Skip Instruction

 SBRS
 Skip the next instruction if a bit in a
register is 1

Example:
sbcs r0, 4
rcall task
nop
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 Skip Instruction

 SBIC/SBIS
 Similar to SBCR/SBCS but checks a bit
from an I/O register

Example:
sbic pinc, 1
mul r0, r1

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 Comparison Instruction

 CP
 Performs comparison of two register
 Content doesn’t change

Example:
ldi r16, 100
ldi r17, 200
cp r16, r17

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 Comparison Instruction

 CPC
 Similar to CP but carry is added
Example:
cpc r16, r17 ; r16 – (r17 + C)

CPI
 Comparison of register with constant

Example:
cpi r16, 255 74
 Comparison Instruction

 CPSE
 Compare and skip instruction

Example:
return:
inc r13
cpse r0, r13
rjmp return
sub r0, r13
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 Branch Instruction

 BREQ
 Jump to the specified relative address if
Z=1
Example:
cp r10, r20
breq they_re_equal
nop
they_re_equal:
nop 76
 Branch Instruction

 BRNE
 Jump to the specified relative address if
Z=0
Example:
cp r10, r20
brne different
nop
different:
nop 77
 Bit & bit test Instruction

 SBI/CBI – Set / Clear Bit in register

 LSL/LSR – Logical Shift Left / Right

 ROL/ROR – Rotate Left / Right (thru
Carry bit)
 ASR – Arithmetic Shift Right

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 Bit & bit test Instruction

 SWAP – Swap Nibbles

 BST/BLD – Bit Store / Load

 BSET/BCLR – Set / Clear Status Bits
by number
 SE*/CL* - Set / Clear Status Bits by
name

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 AVR assembly directives

 .def temp = r16

 register r16 renamed to temp
 .equ tconst = 100
 Defining a constant value

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 AVR assembly directives

 .org $0046
 defining the memory address of the next
instruction
 M_LOOP:
 Label (e.g. for jumps)

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