DeMultiplexing of Address

Bus of 8085
 Procedure For DeMultiplexing AD0–AD7
Bus
• Whenever an instruction is executed by MPU first of
all MPU sends ALE signal to address latch IC to
enable all D Latches to receive new address from
MPU.
• In first T state Microprocessor generates the address
on Address Bus, half portion of address (lower order
address) is generated on AD0-AD7 . This Address bits
are captured by D latches and stored in.
• During next cycles say T2, T3 and so on, MP can use
AD0-AD7 as Data Bus to send receives data. During
this period the initially generated Address is also
available at output pins of D Latches .The IC
74LS373is used as Address Latch it contains 8 D
Latches to store lower half of address.(8 bits).
DeMultiplexing AD0–AD7 Bus
 Demultiplexing AD7-AD0
8085
A15-A8

ALE

AD7-AD0 Latch
A7- A0

D7- D0

– Given that ALE operates as a pulse during

T1, we will be able to latch the address.
Then when ALE goes low, the address is
saved and the AD7– AD0 lines can be
used for their purpose as the bi-directional
data lines.
 Generating Control Signals
• The 8085 generates a single RD signal. However, the signal needs
to be used with both memory and I/O. So, it must be combined with
the IO/M signal to generate different control signals for the memory
and I/O.
– Keeping in mind the operation of the IO/M signal we can use the
following circuitry to generate the right set of signals:
 Control and Status Signals
• Signals:
– RD – Read (active low). To indicate that the I/O or
memory selected is to be read and data are available
on the bus.
– WR – Write: Active low. This is to indicate that the
data available on the bus are to be written to memory
or I/O ports.
– IO/M – To differentiate I/O operation of memory
operations.
• ‘0’ - indicates a memory operation.
• ‘1’-indicates an I/O operation.
– IO/M combined with RD and WR to generate I/O and
memory control signals.
– S1 and S0: Status signals, similar to IO/M, can identify
various operations as shown on the following table :
Control and Status Signals.