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Chapter 41
Chapter 41
Combinational Circuits
Combinational
n inputs • • m outputs
• Circuits •
• •
When input changes, output may change (after a delay)
Combinational Circuits
Analysis
● Given a circuit, find out its function
A
B
C
A
F1
?
B
C
A
B
?
● Function may be expressed as:
A
F2
C
B
C
♦ Boolean function
♦ Truth table
Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
?
♦ Truth table
Design Procedure
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code
4-bits 4-bits
0-9 values
? Value+3
Binary Adder
Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0 C
y
Binary Adder
Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x y z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
Binary Adder
Full Adder
x S
y HA HA
z C
x
S
y
C
z
Subtractors
Half-Subtractor
Full-Subtractor
Half Subtractor
x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
Analysis Procedure
A
F2
C
AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Analysis Procedure
A =0 0 0
F2
C =0
B =0 0
C =0
Analysis Procedure
A =0 0 0
F2
C =1
B =0 0
C =1
Analysis Procedure
A =0 0 0
F2
C =0
B =1 0
C =0
Analysis Procedure
A =0 0 1
F2
C =1
B =1 1
C =1
Analysis Procedure
A =1 0 0
F2
C =0
B =0 0
C =0
Analysis Procedure
A =1 1 1
F2
C =1
B =0 0
C =1
Analysis Procedure
B =1 0
C =0
Analysis Procedure
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
MULTILEVEL NAND CIRCUITS
F=(A+B’)(CD+E)
MULTILEVEL NOR CIRCUITS
F=A(B+CD)+BC’