Slides 11

Design
Methodologies
Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
Design Methodology
• Design process traverses iteratively between three abstractions:

behavior, structure, and geometry
• More and more automation for each of these steps

Design Analysis and Verification
 Accounts for largest fraction of design time

 More efficient when done at higher levels of
abstraction - selection of correct analysis
level can account for multiple orders of
magnitude in verification time
 Two major approaches:
» Simulation
» Verification

Digital Data treated as Analog Signal
VD D
Sp
Vin Vou t
5.0
Bp
3.0
Vo ut (V)
Gn ,p
In D n,p Out tpHL
1.0
Bn
Sn
–1.0
0 0.5 1 1.5 2
t (nsec)
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation)
Representing Data as Discrete Entity
V 0 1 0 VDD
VM Rp
t1 t2 t
CL
Discretizing the data using

switching threshold Rn
The linear switch model

of the inverter

Circuit versus Switch-Level Simulation
5.0
CIN OUT[2]
Circuit
3.0
OUT[3]
1.0
–1.0
0 5 10 15 20
time (nsec)
Switch

Structural Description of Accumulator
entity accumulator is
port ( -- definition of input and output terminals
DI: in bit_vector(15 downto 0) -- a vector of 16 bit wide
DO: inout bit_vector(15 downto 0);
CLK: in bit
);
end accumulator;
architecture structure of accumulator is

component reg -- definition of register ports
port (
DI : in bit_vector(15 downto 0); Design defined as composition of
DO : out bit_vector(15 downto 0);
CLK : in bit register and full-adder cells (“netlist”)
);
end component;
component add -- definition of adder ports
port ( Data represented as {0,1,Z}
IN0 : in bit_vector(15 downto 0);
IN1 : in bit_vector(15 downto 0);
OUT0 : out bit_vector(15 downto 0)
); Time discretized and progresses with
end component;
-- definition of accumulator structure unit steps
signal X : bit_vector(15 downto 0);
begin
add1 : add
port map (DI, DO, X); -- defines port connectivity
reg1 : reg
port map (X, DO, CLK);
Description language: VHDL
end structure; Other options: schematics, Verilog

Behavioral Description of Accumulator
entity accumulator is
port (
DI : in integer;
DO : inout integer := 0;
CLK : in bit
); Design described as set of input-output
end accumulator;
relations, regardless of chosen
architecture behavior of accumulator is implementation
begin
process(CLK)
variable X : integer := 0; -- intermediate variable
begin
if CLK = '1' then Data described at higher abstraction
X < = DO + D1; level (“integer”)
DO <= X;
end if;
end process;
end behavior;

Behavioral simulation of accumulator
Discrete time
Integer data
(Synopsys Waves display tool)

Timing Verification
Critical path
Enumerates and rank

orders critical timing paths
No simulation needed!
(Synopsys-Epic Pathmill)

Issues in Timing Verification
In
4-bit adder
Out
MUX
bypass
False Timing Paths

Implementation Methodologies
Digital Circuit Implementation Approaches
Custom Semi-custom
Cell-Based Array-Based
Standard Cells Macro Cells Pre-diffused Pre-wired

Compiled Cells (Gate Arrays) (FPGA)

Custom Design –
Layout Editor
Magic Layout Editor

(UC Berkeley)
Symbolic Layout
VDD 3
In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program
GND
Stick diagram of inverter

Cell-based Design (or standard cells)
Logic Cell
Feedthrough Cell
Routing
Channel
Rows of Cells
Routing channel
requirements are
reduced by presence
Functional of more interconnect
Module layers
(RAM,
multiplier, )

Standard Cell — Example
[Brodersen92]

Standard Cell - Example
3-input NAND cell

(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies

Automatic Cell Generation
Random-logic layout
generated by CLEO
cell compiler (Digital)

Module Generators —
Compiled Datapath
bus0
buffer
adder
bus2
mux
reg0
bus1 reg1
routing area feed-through bit-slice
Advantages: One-dimensional placement/routing problem

Macrocell Design Methodology
Macrocell
Floorplan: Interconnect Bus

Defines overall
topology of design,
relative placement of
modules, and global
routes of busses, Routing Channel
supplies, and clocks

Macrocell-Based Design
Example
SRAM
SRAM Data paths
Standard cells
Video-encoder chip
[Brodersen92]

Gate Array — Sea-of-gates
polysilicon
VD D
metal
rows of Uncommited
uncommitted possible
cells GND contact Cell
In1 In2 In3 In4
routing
channel Committed
Cell
(4-input NOR)
Out

Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation Using gate-isolation

Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K

(0.6 mm CMOS)
Prewired Arrays
Categories of prewired arrays (or field-

programmable devices):
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based

Programmable Logic Devices
PLA PROM PAL

EPLD Block Diagram
Primary inputs Macrocell
Courtesy Altera Corp.

Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
Vertical routes
Standard-cell like
floorplan
I/O Buffers
I/O Buffers
Rows of logic modules
Routing channels
I/O Buffers

Interconnect
Programmed interconnection Input/output pin
Cell
Antifuse
Horizontal
tracks
Vertical tracks
Programming interconnect using anti-fuses

Field-Programmable Gate Arrays
RAM-based
CLB CLB
switching matrix
Horizontal
routing
channel
Interconnect point
CLB CLB
Vertical routing channel

RAM-based FPGA
Basic Cell (CLB)
Combinational logic Storage elements
R
A Din R
Any function of up to
B/Q1/Q2 4 variables F D Q1
C/Q1/Q2 F G
CE F
D
A
Any function of up to
B/Q1/Q2 4 variables R
G
F D Q2
C/Q1/Q2
G
D G
CE
E Clock
CE
Courtesy of Xilinx

RAM-based FPGA
Xilinx XC4025

Taxonomy of Synthesis Tasks
Architectural Level Logic Level Circuit Level
Behavioral View
state
0 a
(i: 1..16) :: b
sum = sum*z–1 +
2 1
coeff[i]*In*z–1 c x
3 tp
Architecture Logic Circuit

Synthesis Synthesis Synthesis
Structural View
a 4
mem b
fsm x
c a 2 c
* 1
b 2
D

Design
for Test

Validation and Test of
Manufactured Circuits
Goals of Design-for-Test (DFT)

Make testing of manufactured part swift and
comprehensive
DFT Mantra
Provide controllability and observability
Components of DFT strategy

• Provide circuitry to enable test
• Provide test patterns that guarantee reasonable
coverage

Test Classification
 Diagnostic test
» used in chip/board debugging
» defect localization
 “go/no go” or production test
» Used in chip production
 Parametric test
» x e [v,i] versus x e [0,1]
» check parameters such as NM, Vt, tp, T

Design for Testability
N inputs K outputs
N inputs Combinational K outputs Combinational
Logic Logic
Module Module
M state regs
(a) Combinational function (b) Sequential engine
2N patterns 2N+M patterns
Exhaustive test is impossible or unpractical

Problem:
Controllability/Observability
 Combinational Circuits:
controllable and observable - relatively easy to
determine test patterns
 Sequential Circuits: State!
Turn into combinational circuits or use self-test
 Memory: requires complex patterns
Use self-test

Test Approaches
 Ad-hoc testing
 Scan-based Test
 Self-Test
Problem is getting harder
» increasing complexity and heterogeneous
combination of modules in system-on-a-chip.
» Advanced packaging and assembly techniques
extend problem to the board level

Generating and Validating
Test-Vectors
 Automatic test-pattern generation (ATPG)

» for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output
» majority of available tools: combinational networks only
» sequential ATPG available from academic research
 Fault simulation
» determines test coverage of proposed test-vector set
» simulates correct network in parallel with faulty networks
 Both require adequate models of faults in
CMOS integrated circuits

Fault Models
Most Popular - “Stuck - at” model
0 sa0
(output)
1
sa1 Covers almost all (other)
(input)
occurring faults, such as
opens and shorts.
Z ,  : x1 sa1

 : x1 sa0 or
x1

x2 
x3 x2 sa0
 : Z sa1
Problem with stuck-at model:
CMOS open fault
x1 x2
Z
x1
x2
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short models

This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
Problem with stuck-at model:
CMOS short fault
C D
‘0’
A B Causes short circuit between

‘0’ Vdd and GND for A=C=0, B=1
A C Possible approach:
‘0’
Supply Current Measurement (IDDQ)
but: not applicable for gigascale
‘1’ B D
integration

Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
sa0
1
Fault enabling 1 1
Out
1
1
1 0
Fault propagation
0
Techniques Used: D-algorithm, Podem

Ad-hoc Test
Memory Memory
address
data
address
data
test select
Processor
Processor
I/O bus
I/O bus
Inserting multiplexer improves testability
Scan-based Test
ScanIn ScanOut
Out
In Combinational Combinational
Register
Register
Logic Logic
A B

Polarity-Hold SRL
(Shift-Register Latch)
System Data D
Q
System Clock C
SI L1
Scan Data
Q
Shift A Clock A
SO
Shift B Clock B L2
SO
Introduced at IBM and set as company policy

Scan-Path Register
OUT
SCAN PHI2 PHI1
SCANIN SCANOUT
IN
LOAD KEEP

Scan-based Test —Operation
In 0 In1 In2 In 3
Test Test Test Test Test Test Test Test

ScanIn ScanOut
Latch Latch Latch Latch
Out0 Out1 Out2 Out3
Test
1
2
N cycles 1 cycle N cycles

scan-in evaluation scan-out
Scan-Path Testing
A B
SCANIN
REG[1] REG[0]
REG[2] REG[3]
REG[4]
COMPIN
COMP
SCANOUT
REG[5]
OUT
Partial-Scan can be more effective for pipelined datapaths
Boundary Scan (JTAG)
Printed-circuit board
Logic Packaged IC
normal interconnect
Scan-in si so
Scan-out
scan path
Bonding Pad
Board testing becomes as problematic as chip testing

Self-test
(Sub)-Circuit
Stimulus Generator Under Response Analyzer
Test
Test Controller
Rapidly becoming more important with increasing

chip-complexity and larger modules

Linear-Feedback Shift Register (LFSR)
R R R
S0 S1 S2
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0
Pseudo-Random Pattern Generator

Signature Analysis
In
Counter
Counts transitions on single-bit stream

 Compression in time

BILBO
D0 D1 D2
B0
B1
ScanIn ScanOut
mux
R R R
S0 S1 S2
B0 B1 Operation mode
1 1 Normal
0 0 Scan
1 0 Pattern generation or
Signature analysis
0 1 Reset

BILBO Application
ScanIn ScanOut
In Combinational Combinational Out
BILBO-B
BILBO-A
Logic Logic

Memory Self-Test
data -in
data-out
Memory Signature
FSM
Analysis
Under Test
address &
R/W control
Patterns: Writing/Reading 0s, 1s,

Walking 0s, 1s
Galloping 0s, 1s

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Design

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

• Design process traverses iteratively between three abstractions:

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

 Accounts for largest fraction of design time

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Discretizing the data using

The linear switch model

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

architecture structure of accumulator is

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

(Synopsys Waves display tool)

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Enumerates and rank

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Circuit Implementation Approaches

Standard Cells Macro Cells Pre-diffused Pre-wired

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Magic Layout Editor

Stick diagram of inverter

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

3-input NAND cell

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

routing area feed-through bit-slice

Advantages: One-dimensional placement/routing problem

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Floorplan: Interconnect Bus

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

SRAM Data paths

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

In1 In2 In3 In4

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Using oxide-isolation Using gate-isolation

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

LSI Logic LEA300K

Categories of prewired arrays (or field-

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

PLA PROM PAL

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Courtesy Altera Corp.

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Vertical routing channel

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Architecture Logic Circuit

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Goals of Design-for-Test (DFT)

Components of DFT strategy

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995

(a) Combinational function (b) Sequential engine

2N patterns 2N+M patterns

Exhaustive test is impossible or unpractical

Digital Integrated Circuits Design Methodologies © Prentice Hall 1995