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A sign-magnitude Signed-
number Z can be Number
Magnitude
represented as (As,
A) where As is the +3 0 11
sign of Z and A is the +2 0 10
magnitude of Z.
+1 0 01
The leftmost
position, As, is the +0 0 00
sign bit. -0 1 00
The sign bit is either
positive = 0 or -1 1 01
negative = 1 -2 1 10
-3 1 11
Eight Conditions for Signed-
Magnitude Addition/Subtraction
ADD SUBTRACT Magnitudes
Operation Magnit
udes A>B A<B A=B
(+A) + (+B) + (A + B)
(+A) + (-B) + (A – B ) - (B – A ) + (A – B )
(-A) + (+B) - (A – B ) + (B – A ) + (A – B )
(-A) + (-B) - ( A + B)
(+A) - (+B) + (A – B ) - (B – A ) + (A – B )
(+A) - (-B) + (A + B)
(-A) - (+B) - ( A + B)
(-A) - (-B) - (A – B ) + (B – A ) + (A – B )
Examples
Example of adding two +3 0 011
magnitudes when
the result is the sign
+ +2 0 010
of both operands: +5 0 101
Bs = Bs’
As = Bs
A> B Ar = A + B
Ars = As
Ar = A – B
A= B Ars = As
Ar = B – A Ar = 0
Ars = Bs Ars = 0
Done
Summary of Addition and Subtraction
with Signed-Magnitude Data
The signs use an exclusive OR gate where if
the output is 0, then the signs are the same.
Hence, add the magnitudes of the same signed
numbers. If the sum is an overflow, then a
carry is stored in E where E = 1 and
transferred to the flip-flop AVF, add-overflow.
Otherwise, the signs are opposite and
subtraction is initiated and stored in A.
No overflow can occur with subtraction so the
AVF is cleared.
If E = 1, then A > B.
However, if A = 0, then A = B and the sign is
made positive.
If E = 0, then A < B and sign for A is
complemented.
Addition and Subtraction with Signed-
Magnitude Data Hardware Design
Bs B register
Mode
Control
AVF Complementer M
E Parallel Adder
Input
Output Carry
S
Carry
As A register Load
Sum