Professional Documents
Culture Documents
1
Programa
1 - Silício, SiGe, strained Si
1.1 - Introdução A1
1.2 - Propriedades estruturais A1
1.3 - Propriedades térmicas, mecânicas e vibracionais. A1
1.4 - Estrutura de bandas A2
1.5 - Propriedades elétricas e ópticas A2
1.6 - Propriedades de superfície A3
1.7 - Relevância dessa classe de materiais para dispositivos
eletrônicos. A3
2
Introdução
Electronic Equipment
©NOKIA MEGATRENDS.PPT / 16.11.1998EKu
/ page: 6
$ 1000 billion / + 8% *)
Semiconductors
$ 250 billion /+15 % *)
Silicon Wafers
$ 8 billion /+13 % *)
Polysilicon
$ 0,7 billion
+14 % *)
*)
1970-2003
CAGR
3
4
5
6
7
8
What is a Semiconductor?
• Low resistivity => “conductor”
• High resistivity => “insulator”
• Intermediate resistivity => “semiconductor”
– Generally, the semiconductor material used in
integrated-circuit devices is crystalline
• In recent years, however, non-crystalline semiconductors
have become commercially very important
Elemental:
Compound:
10
The Silicon Atom
• 14 electrons occupying the 1st 3 energy levels:
– 1s, 2s, 2p orbitals filled by 10 electrons
– 3s, 3p orbitals filled by 4 electrons
To minimize the overall energy, the 3s and 3p
orbitals hybridize to form 4 tetrahedral 3sp orbitals
Each has one electron and
is capable of forming a bond
with a neighboring atom
11
12
13
14
15
The Si Crystal
“diamond cubic” lattice
• Each Si atom has 4
nearest neighbors
• lattice constant
= 5.431Å
Coordination Number: 4
# atoms in the unit cell: 8
16
Crystal structure Diamond Crystal structure Diamond
7 7
Group of symmetry Oh - Fd3m Group of symmetry Oh -Fd3m
3 22 3 22
Number of atoms in 1 cm 4.4·10 Number of atoms in 1 cm 5·10
-30 6 -30 6 -1
Auger recombination coefficient 10 cm /s Auger recombination coefficient Cn 1.1·10 cm s
-31 6 -1
Debye temperature 374 K Auger recombination coefficient Cp 3·10 cm s
3
Density 5.3234 g/cm Debye temperature 640 K
-3
Dielectric constant 16.2 Density 2.329 g cm
17
Thermal properties
11 - 11
Bulk modulus 7.5·10 dyn cm Bulk modulus 9.8·10
2 2
Melting point 937 °C dyn/cm
Melting point 1412 °C
-1 -1 -1 -1
Specific heat 0.31 J g °C Specific heat 0.7 J g °C
-1 -1 -1 -1
Thermal conductivity 0.58 W cm °C Thermal conductivity 1.3 W cm °C
2 -1 2
Thermal diffusivity 0.36 cm s Thermal diffusivity 0.8 cm /s
-6 -1 -6 -1
Thermal expansion, linear 5.9·10 °C Thermal expansion, linear 2.6·10 °C
18
Thermal properties
19
Thermal properties
20
Mechanical properties
11 2
11 - Bulk moduluss 9.8·10 dyn/cm
Bulk modulus 7.5·10 dyn cm
2 3
-3 Density 2.329 g/cm
Density 5.323 g cm
Hardness 7 on the Mohs scale
Hardness on the Mohs scale 6
2
-2 Surface microhardness (using Knoop's pyramid test) 1150 kg/mm
Surface microhardness (using Knoop's pyramid test) 780 kg mm
Cleavage plane { 111 }
Cleavage plane { 001 }
300 K 300 K
C11 = 12.60·1011 dyn cm-2 C11 = 16.60·1011 dyn/cm2,
C12 = 4.40·1011 dyn cm-2 C12 = 6.40·1011 dyn/cm2
C44 = 6.77·1011 dyn cm-2 C44 = 7.96·1011 dyn/cm2
21
22
23
Wave propagation Wave Character Expression for wave speed Wave speed
direction Wave speed
1/2 5 8.43
[100] VL [C11/ρ] 4.87 ·10
1/2 cm/s 5 5.84
VT [C44/ρ] 3.57 ·10
1/2 cm/s 5 9.13
[110] Vl [(C11+C12+2C44)/2ρ] 5.36 ·10
1/2 cm/s 5 5.84
Vt|| Vt|| = VT = (C44/ρ) 3.57 ·10
1/2 cm/s 5 4.67
Vt ort; [(C11-C12)/2ρ] 2.77 ·10
1/2 cm/s 5 9.36
[111] V l' [(C11+2C12+4C44)/3ρ] 5.51 ·10
1/2 cm/s 5 5.10
V t' [(C11-C12+C44)/3ρ] 3.06 ·10
cm/s
24
25
Silicon-Germanium
Remarks
27
2 -3
Density Si1-xGex (2.329+3.493x-0.499x )g cm 300 K
-3
Si (x=0) 2.329 g cm 300 K
-3
Ge (x=1) 5.323 g cm 300 K
-2
Surface microhardness Si1-xGex (1150 - 350x) kg mm 300 K,
using Knoop's pyramid test
2
Infrared refractive index n(λ) Si1-xGexSi1-xGex n= 3.42 + 0.37x + 0.22 x 300K
-14 3 -1
Radiative recombination coefficient Si (x=0) 1.1 x 10 cm s 300 K
-14 3 -1
Ge (x=1) 6.4 x 10 cm s 300 K
Ge (x=1) 0.33 mo
Ge (x=1) 0.0430 mo
Si (x=0) 0.234 mo
Ge (x=1) 0.095(7) mo 30 K
Effective mass of conductivity mcc= 3/(1/ml+2/mt) Si1-xGex 0.26mo 300K, x < 0.85
-1 -1
Si (x=0) 1.3 W cm K 300 K
-1 -1
Ge (x=1) 0.58 W cm K 300 K
2 -1
Thermal diffusivity Si (x=0) 0.8 cm s 300 K
2 -1
Ge (x=1) 0.36 cm s 300 K
-6 -1
Thermal expansion coefficient Si1-xGex α = (2.6 + 2.55x) x 10 K x < 0.85, 300 K
-6 -1
Si1-xGex α = (7.53 - 0.89x) x 10 K x > 0.85, 300 K
30
Intro
Gate
• Processor Speed depends on Source Drain
•Gate length
•Current velocity Gate
Source Drain
Source: AmberWave
32
History of Strained Silicon
• 1991-2001
– MIT professor Gene Fitzgerald develops strained
silicon and founded AmberWave (1998)
• August 2002
– Intel used strained silicon in the HT Prescott P4
Processor
– AMD contracts AmberWave to develop SS
– Other major chip manufactures consider SS
33
How to Induce Strain?
• Mechanical Force
– Difficult to produce a large
amount of strain (only 0.12%)
– Even straining is hard to
accomplish
– Not practical for manufacturing
• Tensile Film
– Increases electron mobility only
• Epitaxial-Strain Inducing templates
34
Epitaxial-Strain Inducing templates
(A) (B)
• (A) Ge is introduced into the lattice
• aSiGe>a Si
• (B) Si is deposited on top of the SiGe.
• Atoms align causing a strain in the lattice.
Source: M.T. Currie, et al., J. Vac. Sci. Technol. B, vol. 19, p. 2268 (2001)
36
Programa
1 - Silício, SiGe, strained Si
1.1 - Introdução A1
1.2 - Propriedades estruturais A1
1.3 - Propriedades térmicas, mecânicas e vibracionais. A1
1.4 - Estrutura de bandas A2
1.5 - Propriedades elétricas e ópticas A2
1.6 - Propriedades de superfície A3
1.7 - Relevância dessa classe de materiais para dispositivos
eletrônicos. A3
37
38
Optical properties
39
40
41
42
43
44
45
How to make strained silicon
(process)
US 6,831,292 B2
Semiconductor Structures Employing Strained Material Layer
with Defined Impurity Gradients and Methods for Fabricating same
46
Why graded SiGe
Source: www.ncl.ac.uk/eece/research/groups/micro/web-sige.pdf
47
Why graded SiGe
48
How does strained silicon works?
Review
Charge Carrier Mobility
e µ = mobility
e = charge
τ = scattering time
m* m* = effective mass
49
Ge Si GaAs
50
Electron mobility
Source: AmberWave
51
Hole mobility
Source: AmberWave
52
53
The System Strained Si on SiGe
[001] a//(x)
a//(x)
strained Si a^(x)
[010]
Si1-xGe x aSiGe(x)
[100] aSiGe(x)
aSiGe(x)
4 2 4
4 2
EG 2
LH HH EG
LH HH LH
SO
HH
SO SO
Cubic Hydrostatic Uniaxial
silicon strain strain
55
Tensile Strain Contribution on Band
Structure
Band Structure
56
Strain Contribution on the Valence Band
0.2
0.0
Si bulk Si/Si0.5Ge0.5
phonon HH 0.1
-0.1
LH
Energy (eV)
E(LH-HH)
Energy (eV)
-0.2 LH 0.0
-0.3 -0.1
SO
HH
-0.4 -0.2
SO
-0.5 -0.3
Unstrained Si Si/SiGe
≈ 86 % in HH
F= 30 kV/cm
58
Transport Results: Quantization
Effects
3.5
3.0
Enhancement factor Low field mobility
2.5
2.0
1.5
1.0
60
• P-type-compressive (SiGe on source and drain)
• N-type-tensile (silicon nitride capping film)
• Intel claims speed increase by 15-20% but
manufacturing cost increase by only 2%
1.00E+06
(#/cm^2)
1.00E+05
1.00E+04
700 750 800 850 900 950
Growth Temperature (ºC)
Source: C.W. Leitz, et al., J. Appl. Phys., vol. 90, p2730 (2001)
62
Dislocation
• Graded layer TDD ~10^5/cm^2 or lower
• Uniform layer TDD~10^9/cm^2
Source: AmberWave
63
Dislocations- current leakage
• Misfit dislocation at
the interface of
Strained silicon and
SiGe when the
strained silicon exceed
the critical thickness
• Acts as dislocation
pipes for off-current
leakage
Source: http://ej.iop.org/links/q52/OzA8pWMYfRCAvCbiyWotgQ/sst4_1_l02.pdf
64
Diffusion of Ge
• High temperature processing steps required
after application of strained layer
• Speeds up the interdiffusion between the
strained layer and underlying material
• In particular, Ge diffuses into the strained
silicon layer, increasing alloy scattering,
affecting the performance
65
Improvements for the Future
• Current technology: 90-nm process nodes
• New Variations: 65 nm and below
• SSOI – Strained Silicon-on-Insulator
• Dual Channel Heterostructure
–Circuits get improved transistors that switch faster
–Lower dynamic and static power
66
What is SSOI?
Source: Amberwave
67
SSOI Fabrication
• Forming strained
silicon on an
insulating substrate
starts with the
deposition of a
graduated strained
layer of silicon
germanium.
• On top of this, a
“relaxed” layer of
SiGe is formed.
• The strained silicon
layer is deposited on
top of the relaxed
layer
Source: IBM
68
SSOI Fabrication Techniques
• Growth of epitaxial silicon-
germanium and silicon layers
• Wafer bonding
• Layer transfer technology
(Smart Cut)
• Trying to eliminate the SiGe
intermediate layer to produce a
true SSOI structure
• Reduce manufacturing
complexity and cost of the
Source: Amberwave
wafers
69
Why use SSOI?
• Due to the layer of insulation between the
devices on the wafer: increases integration
density
• Up to 25% increase for memory or
repetitive structures
• At least 10% increase for logic circuits
70
SSOI Efficiency Benefits
• Using SiGe (20% Ge) increases electron mobility
1.7-1.8 times ~ equivalent to 40% gain of current
• Aiming for a max between ratio of Ion vs. Ioff
• Increasing current that you can work with while
reducing leakage during the off state
• AMD switching to SOI have reported:
38% improvement in dynamic power
46% improvement in static power
~ 50% overall improvement
71
SSOI Cost Benefits
• Cost: SSOI when used to full advantage
enables a simpler CMOS process
• Result: increases the ability to scale thus
greatly reducing cost of products built using
SSOI
72
Dual Channel Heterostructure
Source: Amberwave
73
Why DCH?
• Allow simultaneous integration of hole and
electron channel devices within the same layer
sequence
• Research results have shown great promise for
attaining symmetric electron and hole mobilities
for SiGe-based CMOS applications
• Significant hole mobility enhancements over bulk
Si
74
Programa
1 - Silício, SiGe, strained Si
1.1 - Introdução A1
1.2 - Propriedades estruturais A1
1.3 - Propriedades térmicas, mecânicas e vibracionais. A1
1.4 - Estrutura de bandas A2
1.5 - Propriedades elétricas e ópticas A2
1.6 - Propriedades de superfície A3
1.7 - Relevância dessa classe de materiais para dispositivos
eletrônicos. A3
75
Duvidas ?
76