High-Performance and

Power-Efficient CMOS
Comparators
UNDER GUIDANCE OF :
PROF. B. BHAUMIK

SUBMITTED BY:
SUBHASH KUMAR & GAURAV GUPTA
PROJECT OBJECTIVE
1). For the comparators with longer inputs, circuit complexity increases drastically,
and the operating speed is degraded accordingly. Another way to designing the
comparator is employing a parallel adder .In this approach, the adder becomes the
major factor limiting the operating speed.

2).In this paper, we propose several design techniques for high performance and
power-efficient CMOS comparators. The proposed techniques span from the
microarchitecture to logic and circuit design levels. In the microarchitecture
design, the priority-encoding algorithm is adopted to efficiently implement each
comparison operation in one clock cycle. The critical path is effectively shortened
using the multilevel look-ahead technique.

3) Furthermore , for long comparators, a two-stage pipelined architecture is used to

partition and balance the logic functions into each half of the clock cycle. In the
logic design, the priority-encoding function and some logic functions are merged in
one complex CMOS gate called the magnitude decision module. Such a design not
only improves the operating speed but also makes the circuit more compact and
power efficient.
Numerical example of 4-b priority-encoding-based comparison.
BLOCK DIAGRAM OF A 4-BIT COMPARATOR
Schematic diagram of a 4-b priority-encoding-based CMOS
comparator
(USING CADENCE VIRTUOSO)
Schematic diagram of a 4-b priority-encoding-based CMOS
comparator.
Schematic diagram of the 8-b macro cell
(USING CADENCE VIRTUOSO)
Schematic diagram of the 8-b macro cell
Schematic diagram of a high-performance 64-b comparator.
(using cadence virtuoso)
Block diagram of a high-performance 64-b comparator.
Timing chart of the critical path

AUTHOR’S SIMULATED WAVEFORM:

 RESULTS
COMPLEXITY COMPARISON OF TWO 64-b COMPARATORS

SIMULATION RESULTS OF TWO DIFFERENT 64-b COMPARATORS