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INTERFACING AND
APPLICATIONS OF DSP
PROCESSOR
Unit VIII

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LOGO Synchronous Serial Interface
• The synchronous serial interface of the C54xx DSP allows it to
communicate with the serial peripherals.
On the DSP device the DX data line
transmits the serial data to the CODEC,
and the DR receives it from the CODEC.
The receive data is timed with reference to
the clock signal CLKR, and the transmit
data with respect to the clock signal
CLKX. The start of the respective data (the
first bit) is synchronized to the frame sync
signals FSR and FSX. Similar to the DSP
device, the corresponding signal pins are
provided on the CODEC. device.

The timing diagram for the receive operation for the interface. Data reception
starts with the FSR pulse. A bit is received for each clock pulse of the CLKR.
After receiving all bits, 8 in this case, the processor generates a RRDY signal
to indicate that the word of data is ready in the data receive register of the
serial port. The status signal RRDY can be read by the processor to determine
if a word of data has been received.
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 A Multichannel Buffered Serial Port (McBSP)
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• McBSP is a full-duplex synchronous serial port.
• Three such ports are provided on the TMS320C5416 DSP.
• McBSP can be used to interface synchronous serial peripherals such
as a CODEC.

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The incoming data enters the port through the DR line into the
receive shift register, RSR, where it is assembled into a word that
is transferred to receive buffer register, RBR. From the buffer
register it is transferred to the data receive register, DRR.
The DSP processor reads the data from the memory-mapped
register DRR using an internal peripheral data bus. The port
informs the processor about the data in DRR using receive
interrupt request, RINT, or using the DMA signals. The DRR status
is recorded in the serial port control register 1, as the RRDY bit,
so that the processor can determine when the data is ready for
transfer.
The DSP can send the data to the outside world using the
memory-mapped data transmit register, DXR. The data written to
DXR is transferred to the transmit shift register, XSR, for shifting
out 1 bit at a time. The port informs the processor about the data
in DXR using transmit interrupt request, XINT, or using the DMA
signals. The DXR status is recorded in the serial port control
register 2, as the XRDY bit, so that the processor can determine
when the data has been transmitted.
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Company A CODEC Interface Circuit
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The PCM3002 [4] is a CODEC device that can be directly connected
to the synchronous serial port of the DSP. It provides 16/20-bit
oversampling sigma-delta A/D and D/A converters. The maximum
sampling rate that can be implemented with this device is 48 KHz.
The device provides stereo ADC and DAC with single-ended
voltage input and output for the left and right channels. The
CODEC can be programmed for digital de-emphasis, digital
attenuation, soft mute, digital loop-back, and the power-down
mode for the ADC and the DAC.

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LOGO • An analog signal is applied to the combination of a delta-sigma
modulator and a decimation filter to convert it to a corresponding
digital signal. The input signal is sampled at a 64X oversampling
rate, eliminating the need for a sample-and-hold circuit and also
simplifying the need for an antialiasing filter. A decimation filter is
used to reduce the digital data rate to the sampling rate before
generating the output bitstream. A highpass filter removes the dc
components of the signal.
• The delta-sigma modulator in conjunction with an interpolation
filter forms the DAC, which converts the serial digital signal to the
corresponding analog signal. The interpolation filter is used to
increase the sampling rate to the one needed by the modulator.
The converted signal is filtered with an analog lowpass filter to
generate the analog output.

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Company PCM3002 CODEC interfacing with the C5416 DSK board
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• The CPLD on the DSK provides the system clock and the other timing
signals for the mode control interface. It also controls the choice of using
the McBSP2 port on the DSP for connection either to the host PC (HPI) or
to the PCM3002. The CPLD has user-accessible registers that can be
loaded to define the various parameters of the CODEC data and control
interfaces .

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• The data interface of the CODEC and the DSP is by way of DIN for data
input, DOUT for data output, BCKIN for data bit clock, and LRCIN for
frame sync signal for the left and right channels. The data bit clock and the
frame sync signals are generated by the CPLD from the CODEC_CLK and
applied to the CODEC and the DSP.
• The system clock for generating various timing signals for the CODEC is
its SYSCLK. This clock must be 256fs, or 384fs, or 512fs, where fs is the
sampling frequency. The CODEC detects the system clock and uses it to
generate the internal dock at 256fs for the digital filters and delta-sigma
modulators.
• The frequency of the LRCIN signal is the ADC/DAC sampling frequency.
The bits are transferred using the bit clock BCLKIN. In the CPLD, the
BCKIN and LRCIN are generated from the 12.228-MHz oscillator dock
called the CODEC_CLK, which is also the default CODEC_SYSCLK,
applied to the CODEC device. The corresponding default bit clock BCLKIN
frequency is 3.0122 MHz (or one-fourth of the CODEC_SYSCLK), and the
sampling frequency is 48 KHz. The default frequencies can be changed by
dividing the CODEC_CLK by 2, 4, 6, or 8. This provides the capability to
change the sampling rate to one of five rates, the smallest being 6 KHz
and the largest 48 KHz.
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