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Module 1: (7)
Computer Function, Interconnections and Evolution
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Module 2: (8)
Computer Arithmetic
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Module 3: (8)
Processor Organization and Control Unit
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Module 4: (7)
Memory and Parallel Processor Organizations
Unit Outcomes :
On completion of the course, student will be able to –
1. Demonstrate computer architecture concepts related to design of modern
processors and compare various generation of processors.
2. Design arithmetic functional units such as: Adder, Subtractor , Multiplier
and Division units.
3. Obtain the knowledge of processor structure and its functions for internal
designing of processor organization.
4. Design the size of the cache for the various processor organizations.
1/5/2020 COA (CS215A)_S.Y. B. Tech. (CSE) Module_3 (2019-20_T4) 2
Contents
Module_3
Processor Organization and Control Unit
Instruction format
Types of Instruction and operations
Common addressing techniques
Processor Structure and function - Processor and register
organization
Instruction Cycle
Instruction Pipelining
Pipeline Performance
Pipeline Hazards - Structural, Data, Control
Control Unit Operation - The functional requirement of processor
Micro – operation and instruction cycle
Functional Requirements & Operations of the Control Unit
Block diagram of control unit.
Objective :
1. To understand instruction level Parallelism and internal
Processor Organization
Outcomes :
On completion of the course, student will be able to –
1. Obtain the knowledge of processor structure and its
functions for internal designing of processor Organization.
• 0 (zero) addresses
– All addresses implicit
– Uses a stack
– e.g. push a
push b
• 2 addresses
One address doubles as operand and result
a=a+b
Instruction Comment
MOV Y,A Y←A
SUB Y,B Y←Y–B
DIV Y,T Y ← Y ÷T
MOD Explanation
00 Memory Mode, No Displacement
01 Memory Mode, 8-bit Displacement
10 Memory Mode, 16-bit Displacement
11 Register Mode, No Displacement
IN AL, [DX]
OUT [DX], AL
PUSH reg16
POP reg16
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
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Logical
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
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String Manipulation Instructions
Mnemonics: REP, MOVS, MOVSB, MOVSW, CMPS, SCAS, LODS, STOS
Mnemonics Explanation
STC Set CF 1 ;set carry flag
CLC Clear CF 0
CMC Complement carry CF CF/
STD Set direction flag DF 1
CLD Clear direction flag DF 0
STI Set interrupt enable flag IF 1
CLI Clear interrupt enable flag IF 0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
LOCK Lock bus during next instruction
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack
8. String Addressing
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9. Direct I/O port Addressing
MOV CL, DH
2. Immediate Addressing
Adder
Supported combinations:
BX SI + disp
BP DI
Instruction
Opcode Address A
Memory
Operand
Operand
• EA = (R)
• Operand is in memory cell pointed to by contents of register R
Registers
• EA = A + (R)
• Address field hold two values
-A = base value
-R = register that holds displacement or vice versa
Instruction
Opcode Register R Address A
Memory
Registers
• A = base
• R = displacement
• EA = A + R
Fetch
Interrupt Indirect
Execute
dry
• Dryer takes 40 minutes
Time
30 40 20 30 40 20 30 40 20 30 40 20
T
a A
s
k wash, dry, and fold
B
O
wash, dry, and fold
r
C
d
e wash, dry, and fold
r D
Time
30 40 40 40 40 20
T
a A
s wash, dry, and fold • Pipelined laundry takes 3.5
k hours for 4 loads
B
O
r
C
d
e
r D
• Sequencing
-Causing the CPU to step through a series of micro-
operations
• Execution
-Causing the performance of each micro-op
-This is done using Control Signals