Designing with FPGA

SEMINAR
by

SATISH S BHAIRANNAWAR
(satishbhairannawar@gmail.com)

Department of Electronics & Communication

Engineering
Dayanand sagar college of engineering
Bangalore-90
“Education is what remains after one has
forgotten everything he learned in school”

Albert Einstein

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 Devices
• Fixed Function Devices (Function is Fixed).

Adder
Subtractor
Multiplexer
Encoder
Decoder etc..,

• Programmable Logic Devices (Functions may be changed).

PROM
PLAs
PALs “Allows to implement Complex logic
CPLDs function within a single IC”
FPGAs etc..,

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 Digital Circuit Building Blocks
• Gates.
• Flip Flops.
• Multiplexers. Standard Building
• Decoders. Blocks

• Digital Circuit implementation uses standard

Building blocks

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 Implementation Spectrum

Microprocessor Reconfigurable ASIC

Hardware

–ASIC gives high performance at cost of

inflexibility.
–Processor is very flexible but not tuned
to the application.
–Reconfigurable hardware is a nice
compromise.
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Programmable Logic Devices
Classification

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 Popular Programmable Devices
SPLD CPLD FPGA

Density Low Low to Medium Medium to High

Few hundred gates 500 to 12,000 gates 3,000 to 5,000,000 gates
Timing Predictable Predictable Unpredictable
Cost Low Low to Medium Medium to High
Major Lattice Semiconductor Xilinx Xilinx
Vendors Cypress Altera Altera
AMD Actel
Example Lattice Semiconductor Xilinx Xilinx
Devices GAL16LV8 CoolRunner Virtex
GAL22V10 XC9500 Spartan
Cypress
PALCE16V8 Altera Altera
MAX Stratix

Actel
Accelerator

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 PLA with 3 Inputs, 5 Product Terms,
and 4 Outputs

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 Field Programmable Gate Arrays
• FPGAs are Programmable Digital logic Chips.

• Reconfigurable Hardware.

• No Analog FPGAs.

• Already Fabricated Device

.
• Also Called as Programmable ASICs
.
• FPGAs have More logic gates, More Speed, More cost.

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 Advantages of FPGAs
• Standard off the shelf products
• Needs no custom Mask
• Programmable by user several times
• Negligible turn around time ( fast time to
market)
• High flexibility (easy to change designs and
fix errors)
• Cheaper than MPGAs at low volumes
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 Disadvantages of FPGAs
• Less dense than MPGAs (field programmability
means hardware for that is on the chip –
‘wasted resources’)
• Slower than MPGAs i.e. higher delays
(programmable interconnects result in higher
RC)
• Unpredictable delays
• More power
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 Layout of a Typical FPGA

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 Generic Design Flow

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 FPGA Generic Design Flow
• Design Entry:
-Create your design files using: schematic editor or hardware
description language (Verilog, VHDL)
• Design “implementation” on FPGA:
-Partition, place, and route to create bit-stream file
• Design verification:
-Use Simulator to check function,
-other software determines max clock frequency.
-Load onto FPGA device (cable connects PC to development
board)
-check operation at full speed in real environment.
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 How FPGAs work
• Internal logic
• FPGAs are built from one basic "logic-cell",
duplicated hundreds or thousands of time. A
logic-cell is composed of a small lookup table,
some gates and a D-flip-flop. Each logic-cell
then can be connected to other logic-cells
through interconnect resources (wires/muxes
placed around the logic-cells).

• complex logic functions can be created from

each logic cell.
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 Idealized FPGA Logic Block
set by configuration
Logic Block latch
bit-stream

1
INPUTS 4-LUT FF OUTPUT
0

4-input "look up table"

• 4-input look up table (LUT)

– implements combinational logic functions
• Register
– optionally stores output of LUT
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 FPGA-Look-Up Tables
• A LUT can be used to code any boolean function of the
inputs (unlike PLD’s).
• Mainly used in SRAM based FPGA’s to code
combinational logic.

G1
Z
G2
LUT
G3
G4

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 Example: Implementation of a
Combinational Function using 4-Input
LUT
A
B
Out
A B C D Out
C
D 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
Out
0 1 1 0 1
B
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
C 1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
D
1 1 1 1 0

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 Xilinx 3000 Series FPGA

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 Specifications ASIC/FPGA
Design
Flow
High Level Design

Low Level Design

RTL Coding

Functional Verification

Logic Synthesis Gate Level Simulation

Place & Route

Fabrication

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Post Si Validation
 Any Questions

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 Thank You

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