EDA TOOLS

Why EDA?
Imagine a Intel based micro processor
having 1.5 million transistors. Would it be
feasible to design such a complex system
with help of truth table and K-maps?

Obviously Impossible.
Continued
Today’s semiconductors and electronic systems
are complex that designing them would be
impossible without electronic design automation
(EDA). This primer provides a comprehensive
over view of the electronic design process, then
describes how design teams use Cadence tools to
create the best possible design in the least amount
of the time.
 Digital Design Flow
Design Analysis

Design Specification

Verilog/
VHDL
Library Design Implementation using HDL

Std., Cell. Synthesis

Library

Simulation
Look up
Table for
timing Timing Analysis

Tech file Place & Route

For layout
values

Extraction
Tech file
For RC
Parasite Verification
extraction
 Design Analysis

Design Specification
Design Analysis
Design Implementation using HDL
This is a very crucial step in digital
Synthesis design where the design functionality
Simulation is stated.
Timing Analysis
Like if we are making a processor,
Place & Route what type of functionality is expected??
Extraction

Verification
 Design Specification
This step involved stating in definite
Design Analysis
terms the performance of the chip.
Design Specification

Design Implementation using HDL

Like if we are making a processor,
data size, processor speed, special
Synthesis functions, power etc. is clearly stated
Simulation at this point. Also somewhat it is decided,
Timing Analysis
the way to implement the design.

Place & Route So, it deals with architectural part of the

Extraction
design at highest level possible.

Verification
Based on these foundation , the whole
design is built
 HDL
Design Analysis
Hardware Description Language is used
Design Specification
to run the simulations.
Design Implementation using HDL

It is very expensive to build the entire

Synthesis
chip and then verify the performance of
Simulation the architecture. Imagine if after designing
Timing Analysis a chip for a whole year, the chip fabricated,
does not come even closer to the stated
Place & Route
specifications.
Extraction

Verification
 HDL (contd.)
Design Analysis
Hardware description languages provides
Design Specification
a way to implement a design without going
Design Implementation using HDL into much architecture, simulate and verify
the design output and functionality.
Synthesis

Simulation

Timing Analysis For eg. rather than building a mux design

Place & Route
in hardware, we can write verilog code
and verify the output at higher level
Extraction of abstraction.
Verification
Examples of HDL: VHDL, Verilog HDL
 HDL (Contd.)
Design Analysis
At this time we can see the design
Design Specification
in the form of Source Codes.
Design Implementation using HDL

It seems more of the software

Synthesis
visualization of the circuit.
Simulation

Timing Analysis The simulated code is taken to

Synthesis to generate the Logic
Place & Route
Circuit.
Extraction

Verification
 Synthesis
Design Analysis
Imagine the use of K-Maps and Truth
Design Specification
Tables to make and implement a digital
Design Implementation using HDL design.
Synthesis
If you notice, most of the digital designs
Simulation are build up of some basic elements or
Timing Analysis components like gates, registers, counters,
adders, subtractors, comparators, RAM,
Place & Route
ROM etc.
Extraction

It forms the fundamentals of Logic

Verification
Synthesis using EDA tools.
 Synthesis (Contd.)
Design Analysis

Design Specification
Standard Cell Library is the collection
Design Implementation using HDL of such building blocks which comprises
Synthesis
most of the digital designs.
Simulation
These cell libraries are fabrication
Timing Analysis technology specific.
Place & Route

Extraction

Verification
 Synthesis ( Contd.)
Design Analysis
After the RTL simulation, the HDL,
Design Specification
code is taken as input by Synthesis
Design Implementation using HDL Tool and converted to Gate level.
Synthesis
At this stage that the digital design
Simulation becomes dependent on the
Timing Analysis fabrication process.
Place & Route
At the end of this stage, we have
Extraction the logic circuit I.e. in terms of
gates and memories.
Verification
 Synthesis ( Contd.)
Design Analysis
What synthesis does is , when it
Design Specification
encounters a specific construct
Design Implementation using HDL in HDL it replaces it with the
corresponding Standard Cell
Synthesis
Component from the library to
Simulation
build the entire design.
Timing Analysis

Like if we use a for loop , it gets

Place & Route
converted to counter and a
Extraction combinational circuit.
Verification
 Synthesis ( Contd.)
Design Analysis
The output of synthesis is a gate
Design Specification
level netlist.
Design Implementation using HDL

Netlist is an ASCII file which

Synthesis
enlists and indicates the devices
Simulation
and the interconnections between
Timing Analysis them.
Place & Route

Extraction

Verification
 Simulation
Design Analysis
After the netlist is generated as part
Design Specification
of synthesis, this netlist is simulated
Design Implementation using HDL to verify the functionality of this
gate level implementation of design.
Synthesis

Simulation
Till this level we just dealt with
Timing Analysis functionality part. Now each step
onward deals with performance
Place & Route
part too.
Extraction

Verification
 Timing Analysis
Design Analysis
RTL and Gate Level simulation
doesn’t take into account the physical
Design Specification

Design Implementation using HDL time delay in signal propagation from

one device to another and through
Synthesis
the device.
Simulation

Timing Analysis This time delay is dependent on the

fabrication process adopted.
Place & Route

Extraction

Verification
 Timing Analysis (Contd.)
Design Analysis
Each component in standard cell
Design Specification
library is associated with some
Design Implementation using HDL specific delay.
Synthesis
Delay Lookup Tables list the
Simulation
delays associated with the
Timing Analysis components.
Place & Route
Delays are in the form of
Extraction rise time, fall time and turn off
Verification
time delays.
 Timing Analysis (Contd.)
Design Analysis
Most of the digital designs employ
Design Specification
concept of timing by using clocks.
Design Implementation using HDL This makes the circuits synchronous.
Synthesis
Consider an AND gate with two inputs,
Simulation
x and y. If at time t = 1 ns, x is available,
Timing Analysis and y comes 1 ns later, what would be
Place & Route
the output. This mismatch in timing
leads to erroneous performance of design.
Extraction

Verification
 Timing Analysis (Contd.)
Design Analysis

Design Specification

In timing analysis, using Delay

Design Implementation using HDL
Lookup Tables, all the inputs
Synthesis and outputs of components are
Simulation verified with timing introduced.
Timing Analysis

Place & Route

Extraction

Verification
 Place & Route
Design Analysis

Design Specification This is the actual stage where

the design implemented at
Design Implementation using HDL
semiconductor layout level.
Synthesis

Simulation
This the stage which really
requires more knowledge of
Timing Analysis
semiconductor physics than
Place & Route digital design.
Extraction

Verification
 Place & Route (Contd.)
Design Analysis Semiconductor layout has to follow
Design Specification
certain design rules to lay devices
at semiconductor level.
Design Implementation using HDL

Synthesis
These design rules are fabrication
process dependent.
Simulation

Timing Analysis
The layout uses layers as p/n diffusion,
Place & Route nwell, pwell, metals, via, iso etc.
Rules involving min. spacing, and
Extraction
electrical relation between two layers
Verification are known as DESIGN RULES.
 Place & Route (Contd.)
Design Analysis

Design Specification

Design Implementation using HDL

Placement and Routing involves
laying of the devices, placing them
Synthesis
and making interconnection between
Simulation them, following the Design Rules.
Timing Analysis
The result is the design implemented
Place & Route
in the form of semiconductor layers.
Extraction

Verification
 Extraction
Design Analysis
Once the layout is made, there always
Design Specification is parasitic capacitances and resistances
Design Implementation using HDL
associated with the design.

Synthesis This is because of the compact layouts

Simulation to make the chips smaller. More you make
Timing Analysis
compact layout more will it introduce
these parasitic components. These
Place & Route
interferes in the functioning and
Extraction
performance of the circuit in terms of
timing, speed and power consumption.
Verification
 Extraction (Contd.)
Design Analysis
Due to these factors it becomes very
Design Specification much important to extract these devices
Design Implementation using HDL
from layout and check the design for
performance and functionality.
Synthesis

Simulation Extraction would extract from the layout,

Timing Analysis
the devices formed because of junctions
of different semiconductor and metal
Place & Route
layers and the interconnections.
Extraction

Verification
 Verification
Design Analysis

Design Specification

Design Implementation using HDL Verification would either be the

tape out stage of the chip or the stage
Synthesis
where design is again taken back
Simulation
through the same flow for
Timing Analysis optimization or modification.
Place & Route
It verifies the extracted view of the
Extraction chip for performance and functionality.
Verification
Major Companies in EDA Tools

• Cadence Design Systems

• Synopsys
• Avanti
• Tanner
 Cadence
Fact sheet

Cadence is the world's largest provider

of electronic design automation (EDA)
products and services. Our end-to-end
solutions help computer,
communication, and consumer
electronics companies create high-
performance systems and integrated
circuits (ICs) in the shortest possible
time. Cadence is a global company
with 5,700 employees in over 30 major
locations, and revenues of nearly $1.3
billion in 2000.
 History of Cadence

Cadence Design Systems, Inc. was established in 1988

through the merger of two EDA pioneers—ECAD, Inc.
and SDA Systems. Through innovative product
development, strategic partnerships, and highly
successful business mergers, Cadence has become the
industry's leading supplier of EDA software technology
and services.
 Cadence Design Technologies

•System-level Design
•Functional Verification
•Emulation and Acceleration
•Synthesis/Place-and-Route
•Analog, RF, and Mixed-signal Design
•Custom IC Layout
•Physical Verification and Analysis
•IC Packaging
•PCB Design
Cadence Design Flow
Digital Design:

Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification
 NC - Verilog
NC-Family of Simulators
Standard
Cell
Library
NC-Verilog

The Cadence NC family of

Ambit Synthesis
simulators (NC-Sim, NC-
Verilog®, NC-VHDL and the
Pearl Static Timing Analysis
Verilog® and VHDL Desktop
simulators) provides a single-
Silicon Ensemble kernel simulator that can verify
Placement & Route
both mixed-language and mixed-
Hyper Extract Tech. Rules
verification
signal designs.
 NC – Verilog (Contd.)
Advantage
Standard
Cell Works on the principle of Native
Library
NC-Verilog Compilation.

Ambit Synthesis
Unlike other compilers it compiles
HDL code directly to machine
executable codes, rather than going
Pearl Static Timing Analysis
through the intermediate
conversion to C.
Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules
verification
It decreases:
Compilation time, Memory
requirement and use of system
resources
 NC – Verilog (Contd.)
Key Features
Standard
Cell Fastest mixed-language
Library
NC-Verilog simulation available due to unique
NC architecture
Ambit Synthesis

Powerful integrated debug and

analysis environment
Pearl Static Timing Analysis

Mixed-language, mixed-signal,
Silicon Ensemble
Placement & Route
and system-level support
Hyper Extract Tech. Rules
verification
 Ambit Buildgates Synthesis
Key Features
Standard
Cell
Library
NC-Verilog
BuildGates® Synthesis can
synthesize multimillion-gate
Ambit Synthesis
designs very rapidly.

Pearl Static Timing Analysis BuildGates features high-capacity

and high-performance timing
Silicon Ensemble
analysis.
Placement & Route

Hyper Extract Tech. Rules .

verification
 Ambit Buildgates Synthesis

Standard
Cell
Library
NC-Verilog
BuildGates® Synthesis can
synthesize multimillion-gate
Ambit Synthesis
designs very rapidly.

Pearl Static Timing Analysis BuildGates features high-capacity

and high-performance timing
Silicon Ensemble
analysis.
Placement & Route

Hyper Extract Tech. Rules .

verification
 Ambit Buildgates Synthesis
Contd.
Standard
Key Features
Cell
Library
NC-Verilog Provides productive multimillion-
gate synthesis through higher
Ambit Synthesis
capacity and faster runtimes

Delivers accuracy and reduced

Pearl Static Timing Analysis
iterations through integrated sign-
off static timing analysis
Silicon Ensemble
Placement & Route
Reduces IC power consumption
Hyper Extract Tech. Rules
verification
with the Low-power Synthesis
Option

.
 Ambit Buildgates Synthesis
Contd.
Standard
Optimized Design
Cell
Library
NC-Verilog

Ambit Synthesis It can optimize the design for:

• Speed
Pearl Static Timing Analysis • Size
• Power Consumption
.
Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification
 Static Timing Analysis (Pearl)
In this era of high performance
electronics, timing continues to be a top
priority and designers are spending
increased effort addressing IC
performance.

Two Methods are employed for Timing

Analysis:

Dynamic Timing Analysis

Static Timing Analysis
 Static Timing Analysis (Pearl)
(Contd.)
Dynamic Timing Analysis

Traditionally, a dynamic simulator has

been used to verify the functionality and
timing of an entire design or blocks
within the design.

Dynamic timing simulation requires

vectors, a logic simulator and timing
information. With this methodology, input
vectors are used to exercise functional
paths based on dynamic timing
behaviors for the chip or block.
 Static Timing Analysis (Pearl)
(Contd.)
Dynamic Timing Analysis: Limitations
The advent of larger designs and mammoth vector
sets make dynamic simulation a serious bottleneck
in design flows.

Dynamic simulation is becoming more problematic

because of the difficulty in creating comprehensive
vectors with high levels of coverage.

Time-to-market pressure, chip complexity, limitations

in the speed and capacity of traditional simulators --
all are motivating factors for migration towards static
timing techniques.
 Static Timing Analysis (Pearl)
(Contd.)

STA is an exhaustive method of analyzing,

debugging and validating the timing performance of
a design.

First, a design is analyzed, then all possible paths

are timed and checked against the requirements.

Since STA is not based on functional vectors, it is

typically very fast and can accommodate very large
designs (multimillion gate designs).

STA is exhaustive in that every path in the design is

checked for timing violations.
 Static Timing Analysis (Pearl)
(Contd.)
Limitations:

STA does not verify the functionality of a design.

Also, certain design styles are not well suited for
static approach. For instance, dynamic simulation
may be required for asynchronous parts of a design
and certainly for any mixed-signal portions.
Silicon Ensemble
Place & Route
 Future Trends

• Verilog AMS
• CCAR (Cadence Chip Assemble Router)
• VCC
• Testbuilder for Verification
• PKS (Physically Knowledgeable Synthesis)
• ATS