CS 6103 SYSTEM PROGRAMMING

Dr. Shamama Anwar

Assistant Professor
Department of Computer Science and Engineering,
BIT, Mesra
Course Objectives
Upon completing the course, you will be able to learn
following parameters:

• Support, dependency and limitations of system software on available

system architecture.
• Clarity about the concrete view on the theoretical and practical aspects
of system software.
• Understand the working of various system software such as assemblers,
linkers, loaders and macro-processors.
• Ability to design and develop system software (complete life cycle).

2
Syllabus
MODULE – I
• Background: Introduction, System Software and Machine
Architecture, The Simplified Instructional Computer (SIC), Traditional
(CISC) machines, RISC Machines.

MODULE – II & III

• Assemblers: Basic Assembler Functions, Machine – Dependent
Assembler Features, Machine – Independent Assembler Features,
Assembler Design Options, Implementation Examples.

MODULE – IV & V
• Loaders and Linkers: Basic Loader Functions, Machine - Dependent
Loader Features, Machine – Independent Loader Features, Loader
Design Options, Implementation Examples.

3
Syllabus
MODULE – VI
• Macro Processors: Basic Macro Processor Functions, Machine –
Independent Macro Processor Features, Macro Processor Design
Options, Implementation Examples.

MODULE – VII
• Software Engineering Issues: Introduction to Software Engineering
Concepts, System Specifications, Procedural System Design, Object –
Oriented Design, System Testing Strategies.

4
Books
Text Book :
• L. L. Beck – System Software – An Introduction to Systems Programming,
3rd Edn., Pearson Education, New Delhi, 2004.

Reference Book:
• J.J. Donovan – System Programming, McGraw Hill , New Delhi, 1993.
• D.M. Dhamdhere – System Programming and Operating Systems, 2nd
Edn., Tata McGraw Hill , New Delhi, 2000.

5
Marks Distribution
• Mid Semester Examinations : 25 marks
• Assignment : 15 marks
• End Semester Examinations : 60 marks

6
Module - I
1. Introduction
2. System Software and Machine Architecture
3. The Simplified Instructional Computer (SIC)
3.1 SIC Machine Architecture
3.2 SIC/XE Machine Architecture
3.3 SIC Programming Example
4. Traditional (CISC) machines
4.1 VAX Architecture
4.2 Pentium Pro Architecture
5. RISC Machines
5.1 UltraSPARC Architecture
5.2 PowerPC Architecture
5.3 Cray T3E Architecture

7
1. Introduction
• System Software: It consists of a variety of programs that support the operation
of a computer. (compiler, loader, assembler, microprocessor, etc.).

People
Application Programming
Compliers Assemblers Microprocessors
Loaders Text Editors Debugging aids Searching and sorting
Memory Device
I/O Programs File systems Scheduler Libraries Management Management

Foundation of System Programming

8
2. System Software and Machine Architecture
How is System Software different from Application Software ?

Architecture

SIC CISC RISC

SIC SIC/XE VAX Pentium UltraSPARC Cray T3E
Pro PowerPC

9
3. The Simplified Instructional Computer (SIC)
Memory, Registers, Data Formats, Instruction Formats, Addressing Modes,
Instruction Sets, Input and Output

3.1 SIC Machine Architecture

• Memory: 8 bits = byte, 3 bytes = word, Total 215 bytes
• Registers: 5 registers of 24 bits each.
Mnemonic Number Special Use
A 0 Accumulator
X 1 Index register
L 2 Linkage register
PC 8 Program Counter
SW 9 Status word
• Data Formats: Integers – 24 bit (2’s complement for –ve numbers)
Characters – 8 bit ASCII code
Floating point – no representation
10
3. The Simplified Instructional Computer (SIC)
• Instruction Formats:
8 1 15
opcode x address

• Addressing Modes:
Mode Indication Target address calculation
Direct x=0 TA = address
Indexed x=1 TA = address + (X)

LDA TEN 0000 0000 0 001 0000 0000 0000

EA = 1000

STCH BUFFER, X 0101 0100 1 001 0000 0000 0000

EA = 1000 + content of X

11
12
3. The Simplified Instructional Computer (SIC)
• Instruction Set: Load / Store (LDA, LDX, STA, STX)
Arithmetic (ADD, SUB, MUL, DIV)
Compare (COMP)
Jump (JLT, JEQ, JGT)
Subroutine jump (JSUB, RSUB)

• Input / Output: Test Device (TD), Read Data (RD), Write Data (WD)

13
3. The Simplified Instructional Computer (SIC)
3.2 SIC/XE Machine Architecture
• Memory: 8 bits = byte, 3 bytes = word, Total 220 bytes
• Registers: 5 + 4 registers of 24 bits each.
Mnemonic Number Special Use
B 3 Base register
S 4 General register
T 5 General register
F 6 Floating point accumulator (48 bits)

• Data Formats: Integers – 24 bit (2’s complement for –ve numbers)

Characters – 8 bit ASCII code
Floating point – 48 bit
1 11 36
s exponent fraction

14
3. The Simplified Instructional Computer (SIC)
SIC/XE Machine Architecture
• Instruction Formats: 8
Format 1 (1 byte): opcode
4 C
Example: RSUB 0100 1100
8 4 4
Format 2 (2 bytes): opcode r1 r2 A 0 0 4
Example: COMPR A, S 1010 0000 0000 0100

6 1 11 1 1 1 12
Format 3 ( 3 bytes):
opcode n i x b p e disp

Indirect Immediate Indexed Base Relative PC Relative e=0

Format 4 (4 bytes): 6 1 1 1 1 11 20
opcode n i x b p e disp

e=1

15
3. The Simplified Instructional Computer (SIC)
SIC/XE Machine Architecture
• Addressing Modes:
• PC-relative or base-relative addressing mode is preferred over direct
addressing mode.
• Can save one byte from using format 3 rather than format 4.
• Reduce program storage space
• Reduce program instruction fetch time
• Relocation will be easier.

Mode Indication Target address calculation

Base Relative b=1, p=0 TA = (B) + disp (0 ≤ disp ≤ 4095)
PC Relative b=0, p=1 TA = (PC) + disp (-2048 ≤ disp ≤ 2047)

16
 (B) = 006000, (PC) = 003000, (X) = 000090

000000 1 1 0 0 1 0 0110 0000 0000

EA = (PC) + disp = 003000 + 600 = 3600 Content of A = 10300

000000 1 1 1 1 0 0 0011 0000 0000

EA = (B) + disp + X = 006000 + 300 + 90 = 6390 Content of A = 00C303

000000 0 1 0 0 0 0 0000 0011 0000

EA = disp = 30 Content of A = 000030

17
3. The Simplified Instructional Computer (SIC)
SIC/XE Machine Architecture
• Instruction Set: Load / Store
Register Arithmetic (ADDR, SUBR, MULR, DIVR)
Floating point Arithmetic (ADDF, SUBF, MULF, DIVF)
Register Move (RMO)

• Input / Output: Test Device (TD), Read Data (RD), Write Data (WD)

18
3. The Simplified Instructional Computer (SIC)
3.3 SIC Programming Example: (Load / Store)
Load constant 5 into register A Assign the value 5 to a variable
LDA FIVE LDA FIVE
.... STA ALPHA
FIVE WORD 5 ....
ALPHA RESW 1
FIVE WORD 5

Load character ‘Z’ into register A Store character in variable C1

LDCH CHARZ LDCH CHARZ
.... STCH C1
CHARZ BYTE C’Z’ ....
CHARZ BYTE C’Z’
C1 RESB 1

19
3. The Simplified Instructional Computer (SIC)
SIC/XE Programming Example: (Load / Store)
Load constant 5 into register A Assign the value 5 to a variable
LDA #5 LDA #5
STA ALPHA
....
ALPHA RESW 1

Load character ‘Z’ into register A Store character in variable C1

LDA #90 LDA #90
STCH C1
....
C1 RESB 1

20
3. The Simplified Instructional Computer (SIC)
Arithmetic Example:
SIC Programming Example: SIC/XE Programming Example:

BETA = (ALPHA + INCR – 1)

LDA ALPHA LDA ALPHA

ADD INCR LDS INCR
SUB ONE ADDR S,A
STA BETA SUB #1
.... STA BETA
ONE WORD 1 ....
ALPHA RESW 1 ALPHA RESW 1
BETA RESW 1 BETA RESW 1

21
3. The Simplified Instructional Computer (SIC)
Looping Example:
SIC Programming Example: SIC/XE Programming Example:

Copies a String to another

LDX ZERO LDX #0

MOVECH LDCH STR1, X LDT #7
STCH STR2, X MOVECH LDCH STR1, X
TIX SEVEN STCH STR2, X
JLT MOVECH TIXR T
.... JLT MOVECH
ZERO WORD 0 ....
STR1 BYTE C’GOODBYE’ STR1 BYTE C’GOODBYE’
STR2 RESB 7 STR2 RESB 7
SEVEN WORD 7

22
3. The Simplified Instructional Computer (SIC)
Looping Example:
SIC Programming Example: SIC/XE Programming Example:
Add two arrays of size 100
LDA ZERO LDX #0
STA INDEX LDT #300
MOVE LDX INDEX LDS #3
LDA ALPHA, X MOVE LDA ALPHA, X
ADD BETA, X ADD BETA, X
STA GAMMA, X STA GAMMA, X
LDA INDEX ADDR S, X
ADD THREE COMPR X,T
STA INDEX JLT MOVE
COMP K ....
JLT MOVE ....
....
....

23
3. The Simplified Instructional Computer (SIC)
Input / Output Example:
SIC Programming Example: SIC/XE Programming Example:
Read 1 byte of data from device F1 and copy to device 05
INLOOP TD INDEV
JEQ INLOOP
RD INDEV
STCH DATA
OUTLOOP TD OUTDEV
JEQ OUTLOOP
LDCH DATA
WD OUTDEV

INDEV BYTE X’F1’

OUTDEV BYTE X’05’
DATA RESB 1

24
Example
Read Record into Buffer Read Record into Buffer and Subroutine
calculate length
LDX ZERO LDX ZERO RDREC:
RL: TD IP RL: TD IP LDX ZERO
JEQ RL JEQ RL RL: TD IP
RD IP RD IP JEQ RL
COMP ZERO COMP ZERO RD IP
JEQ EXIT JEQ EXIT COMP ZERO
STCH BUFFER, X STCH BUFFER, X JEQ EXIT
TIX MAX TIX MAX STCH BUFFER, X
JLT RL JLT RL TIX MAX
EXIT: EXIT:STX LENGTH JLT RL
EXIT:STX LENGTH
ZERO WORD 0 ZERO WORD 0 RSUB
IP BYTE X’7’ IP BYTE X’7’ ZERO WORD 0
BUFFER RESB 4096 BUFFER RESB 4096 IP BYTE X’7’
MAX WORD 4096 MAX WORD 4096 BUFFER RESB 4096
LENGTH RESW 1 MAX WORD 4096
LENGTH RESW 1

25
Example
Write Record from Buffer Subroutine

LDX ZERO WRREC:

WL: TD OP LDX ZERO
JEQ WL WL: TD OP
LDCH BUFFER, X JEQ WL
WD OP LDCH BUFFER, X
TIX LENGTH WD OP
JLT WL TIX LENGTH
JLT WL
ZERO WORD 0 RSUB
OP BYTE X’3’
BUFFER RESB 4096 ZERO WORD 0
LENGTH RESW 1 OP BYTE X’3’
BUFFER RESB 4096
LENGTH RESW 1

26
Example
COPY: RDREC: WRREC:
STL RADR LDX ZERO LDX ZERO
CL: JSUB RDREC RL: TD IP WL: TD OP
LDA LENGTH JEQ RL JEQ WL
COMP ZERO RD IP LDCH BUFFER, X
JEQ EF COMP ZERO WD OP
JSUB WRREC JEQ EXIT TIX LENGTH
J CL STCH BUFFER, X JLT WL
EF: LDA EOF TIX MAX RSUB
STA BUFFER JLT RL
LDA THREE EXIT:STX LENGTH OP BYTE X’3’
STA LENGTH RSUB
JSUB WRREC
LDL RADR IP BYTE X’7’
RSUB MAX WORD 4096
EOF BYTE C’EOF’
THREE WORD 3
ZERO WORD 0
RADR RESW 1
LENGTH RESW 1
BUFFER RESB 4096 27
4. Traditional (CISC) Machines
4.1 VAX Architecture
• Memory: 8 bits = byte, 2 bytes = word, 4 bytes = long word,
8 bytes = quadword, 16 bytes = octaword.
Virtual address space of 232 bytes (system space and process space)

• Registers: 16 registers of 32 bits each.

Mnemonic Special Use

R0 – R5 General purpose / Machine instructions
R6 – R11 General purpose
R12 Argument Pointer (AP)
R13 Frame Pointer (FP)
R14 Stack Pointer (SP)
R15 Program Counter (PC)

28
4. Traditional (CISC) Machines
• Data Formats: Integers – byte – octaword (2’s complement for –ve numbers)
Characters – 8 bit ASCII code
Floating point – 4 representation ( 4 – 16 bytes)
packed decimal format

• Instruction Formats: variable length instruction format

opcode (1 / 2 byte) , 6 operand specifiers
• Addressing Modes: Register mode, Register deferred mode, auto increment /
auto decrement mode, indirect addressing (base relative,
PC relative)
• Instruction Set: (Operation Type, Operand Data type, No. of operands)
ADDW2, MULL3, CVTWL

• Input / Output: I/O device controller

29
4. Traditional (CISC) Machines
4.2 Pentium Pro Architecture
• Memory: 8 bits = byte, 2 bytes = word, 4 bytes = double word,
Segments (segment no. , offset), Pages
• Registers: registers of 32 bits each.
Mnemonic Special Use
EAX, EBX, ECX, EDX General purpose (data manipulation)
ESI, EDI, EBP, ESP General purpose (address)
EIP Pointer to the next instruction
FLAGS Status, comparison and arithmetic result
CS Segment register (address of currently executing code
segment)
SS Segment register (address of current stack segment)
DS, ES, FS, GS Segment registers (address od data segments)
FPU Floating point unit (8 80 bit data registers)

30
4. Traditional (CISC) Machines
• Data Formats: Integers – 8, 16 , 32 bit (2’s complement for –ve numbers), also
supports BCD
Characters – 8 bit ASCII code
Floating point – 4 representation ( 4 – 16 bytes)
packed decimal format

• Instruction Formats: variable length instruction format (1 – 10 bytes)

opcode (1 / 2 byte) , operand specifiers, addressing mode

• Addressing Modes: Immediate mode, Register mode, Direct mode, Relative

mode
• Instruction Set: Register to Register, Register to Memory, Memory to Memory
Zero, one , two or three operand instruction
• Input / Output: I/O port to EAX register / EAX register to I/O port

31
5. RISC Machines
5.1 UltraSPARC Architecture (Scalable Processor Architecture)
• Memory: 8 bits = byte, 2 bytes = half word, 4 bytes = word
8 bytes = doubleword
Virtual address space of 264 bytes (pages)

• Registers: registers of 32 bits each.

Mnemonic Special Use
r0 – r7 Global registers (r0 contains value zero)
r8 – r31 General purpose (with overlapping usage)
FPU Floating Point Unit (64 bit)

• Data Formats: Integers – 8, 16 , 32, 64 bit (2’s complement for –ve numbers),
Characters – 8 bit ASCII code
Floating point – 3 representation: single precision (32 bits)
1 8 23
s exponent fraction
32
5. RISC Machines
• Data Formats: Floating point – double precision (64 bits)
1 11 52
s exponent fraction
quad precision (96 bits)
1 15 80
s exponent fraction

• Instruction Formats: 3 instruction formats (32 bits)

Format 1: Call instructions
Format 2: Branch instructions
Format 3: (Register and Arithmetic instructions)

33
5. RISC Machines
• Addressing Modes: Immediate mode, Register mode, PC Relative mode,
Register indirect with displacement, Register indirect indexed

• Instruction Set: Register to Register, Register to Memory, pipelined instructions

delayed branches, stall
• Input / Output: no special I/O instructions are needed.

34
5. RISC Machines
5.2 PowerPC Architecture
• Memory: 8 bits = byte, 2 bytes = half word, 4 bytes = word
8 bytes = doubleword, 16 bytes = quadword
Virtual address space of 264 bytes (segment, pages)

• Registers: 32 registers of 64 bits each.

Mnemonic Special Use
GPR0 – GPR31 General purpose
FPU Floating Point Unit (32 64 bit register)
CR Control register
LR Link Register
CR Count Register
MSR Machine Status Register

35
5. RISC Machines
• Data Formats: Integers – 8, 16 , 32, 64 bits (2’s complement for –ve numbers),
Characters – 8 bit ASCII code
Floating point – 2 representation: single precision (32 bits)
1 8 23
s exponent fraction

Floating point – double precision (64 bits)

1 11 52
s exponent fraction

• Instruction Formats: 7 instruction formats (32 bits)

36
5. RISC Machines
• Addressing Modes: Immediate mode, Register direct mode, Memory access
(Register indirect, register indirect with index, register indirect
with immediate index), Branch instruction (Absolute, Relative,
Link Register, Count Register)

• Instruction Set: Load / Store, register arithmetic, floating point arithmetic

• Input / Output: 2 different methods: Direct store segments, Virtual memory access

37
5. RISC Machines
5.3 Cray T3E Architecture
• Memory: Each PE has its own local memory (64MB – 2GB)
System memory is logically shared.

• Registers: registers of 64 bits each.

Mnemonic Special Use
R0 – R31 General purpose
R31 Zero
F0 – F31 Floating point registers
F31 Zero
PC Program Counter

38
5. RISC Machines
• Data Formats: Integers – long / quadwords(2’s complement for –ve numbers),
Characters – 8 bit ASCII code
Floating point – 2 representation

• Instruction Formats: 5 instruction formats (32 bits)

• Addressing Modes: Immediate mode, Register direct mode, PC relative, Register

indirect with displacement
• Instruction Set: 130 machine instructions (no byte operations)

• Input / Output: multiple I/O ports

39